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Texas Instruments 28xxx Reference Manual

Texas Instruments 28xxx Reference Manual

Texas instruments enhanced pulse width modulator (epwm) reference guide
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TMS320x28xx, 28xxx Enhanced Pulse
Width
Modulator (ePWM) Module
Reference Guide
Literature Number: SPRU791D
November 2004 – Revised October 2007

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  • Page 1 TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide Literature Number: SPRU791D November 2004 – Revised October 2007...
  • Page 2 SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Preface Introduction Introduction Submodule Overview Register Mapping ePWM Submodules Overview Time-Base (TB) Submodule 2.2.1 Purpose of the Time-Base Submodule 2.2.2 Controlling and Monitoring the Time-base Submodule 2.2.3 Calculating PWM Period and Frequency 2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules 2.2.5 Time-base Counter Modes and Timing Waveforms Counter-Compare (CC) Submodule...
  • Page 4 Controlling Multiple Buck Converters With Same Frequencies Controlling Multiple Half H-Bridge (HHB) Converters Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) Practical Applications Using Phase Control Between PWM Modules Controlling a 3-Phase Interleaved DC/DC Converter Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter Registers Time-Base Submodule Registers Counter-Compare Submodule Registers...
  • Page 5 Multiple ePWM Modules Submodules and Signal Connections for an ePWM Module ePWM Submodules and Critical Internal Signal Interconnects Time-Base Submodule Block Diagram Time-Base Submodule Signals and Registers Time-Base Frequency and Period Time-Base Counter Synchronization Scheme 1 Time-Base Counter Synchronization Scheme 2 Time-Base Counter Synchronization Scheme 3 Time-Base Up-Count Mode Waveforms Time-Base Down-Count Mode Waveforms...
  • Page 6 2-43 Event-Trigger SOCB Pulse Generator Simplified ePWM Module EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave Control of Four Buck Stages. Here F Buck Waveforms for Figure 3-3 (Note: Only three bucks shown here) Control of Four Buck Stages. (Note: F Buck Waveforms for Figure 3-5 (Note: F Control of Two Half-H Bridge Stages (F Half-H Bridge Waveforms for Figure 3-7 (Note: Here F...
  • Page 7 ePWM Module Control and Status Register Set Grouped by Submodule Submodule Configuration Parameters Time-Base Submodule Registers Key Time-Base Signals Counter-Compare Submodule Registers Counter-Compare Submodule Key Signals Action-Qualifier Submodule Registers Action-Qualifier Submodule Possible Input Events Action-Qualifier Event Priority for Up-Down-Count Mode Action-Qualifier Event Priority for Up-Count Mode 2-10 Action-Qualifier Event Priority for Down-Count Mode...
  • Page 8 List of Tables SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback...

  • Page 9: Related Documentation From Texas Instruments

    ADC module, which is a 12-bit pipelined ADC. SPRU791— TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motor control,...
  • Page 10 Related Documentation From Texas Instruments SPRU790— TMS320x28xx, 28xxx Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide describes the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine in high performance motion and position control systems.
  • Page 11 (DAC). SPRAAH1— Using the Enhanced Quadrature Encoder Pulse (eQEP) Module of the eQEP module as a dedicated capture unit and is applicable to the TMS320x280x, 28xxx family of processors. SPRA820— Online Stack Overflow Detection on the TMS320C28x DSP online stack overflow detection on the TMS320C28x™...
  • Page 12 Read This First SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback...

  • Page 13: Introduction

    The enhanced pulse width modulator (ePWM) peripheral is a key element in controlling many of the power-related systems found in both commercial and industrial equipments. These systems include digital motor control, switch mode power supply control, uninterruptible power supplies (UPS), and other forms of power conversion.

  • Page 14: Introduction

    PWM outputs. This extension is the high-resolution pulse width modulator (HRPWM) and is described in the TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (SPRU924). See the device-specific data manual to determine which ePWM instances include this feature.

  • Page 15: Multiple Epwm Modules

    www.ti.com EPWM1INT EPWM1SOC To eCAP1 EPWM2INT EPWM2SOC EPWMxINT EPWMxSOC The order in which the ePWM modules are connected may differ from what is shown in Section 2.2.3.2 for the synchronization scheme for a particular device. Each ePWM module consists of seven submodules and is connected within a system via the signals shown in SPRU791D –...

  • Page 16: Submodules And Signal Connections For An Epwm Module

    Submodule Overview Figure 1-2. Submodules and Signal Connections for an ePWM Module EPWMxSYNCI EPWMxSYNCO EPWMxTZINT EPWMxINT EPWMxSOCA EPWMxSOCB Peripheral bus Figure 1-3 shows more internal details of a single ePWM module. The main signals used by the ePWM module are: PWM output signals (EPWMxA and EPWMxB).

  • Page 17: Register Mapping

    www.ti.com Figure 1-3. ePWM Submodules and Critical Internal Signal Interconnects Time-base (TB) TBPRD shadow (16) TBPRD active (16) Counter TBCTL[PHSEN] UP/DWN (16 bit) CTR = ZERO TBCTR active CTR_Dir (16) TBPHS active (16) Counter compare (CC) CTR = CMPA CMPA active (16) CMPA shadow (16) CTR = CMPB CMPB active (16)

  • Page 18: Epwm Module Control And Status Register Set Grouped By Submodule

    These registers are only available on ePWM instances that include the high-resolution PWM extension. Otherwise these locations are reserved. These registers are described in the TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (SPRU924). See the device specific data manual to determine which instances include the HRPWM.

  • Page 19: Epwm Submodules

    Seven submodules are included in every ePWM peripheral. Each of these submodules performs specific tasks that can be configured by software. Topic Overview Time-Base (TB) Submodule Counter-Compare (CC) Submodule Action-Qualifier (AQ) Submodule Dead-Band Generator (DB) Submodule PWM-Chopper (PC) Submodule Trip-Zone (TZ) Submodule Event-Trigger (ET) Submodule SPRU791D –...

  • Page 20: Overview

    Overview Overview Table 2-1 lists the seven key submodules together with a list of their main configuration parameters. For example, if you need to adjust or control the duty cycle of a PWM waveform, then you should see the counter-compare submodule in Table 2-1.
  • Page 21 www.ti.com Table 2-1. Submodule Configuration Parameters (continued) Submodule Configuration Parameter or Option Event-trigger (ET) Enable the ePWM events that will trigger an interrupt. Enable ePWM events that will trigger an ADC start-of-conversion event. Specify the rate at which events cause triggers (every occurrence or every second or third occurrence) Poll, set, or clear event flags Code examples are provided in the remainder of this document that show how to implement various...
  • Page 22 Overview Example 2-1. Constant Definitions Used in the Code Examples (continued) #define DB_ACTV_LO // PCCTL (chopper control) // = = = = = = = = = = = = = = = = = = = = = = = = = = // CHPEN bit #define CHP_ENABLE...

  • Page 23: Time-Base (Tb) Submodule

    www.ti.com Time-Base (TB) Submodule Each ePWM module has its own time-base submodule that determines all of the event timing for the ePWM module. Built-in synchronization logic allows the time-base of multiple ePWM modules to work together as a single system. Figure 2-1.

  • Page 24: Controlling And Monitoring The Time-Base Submodule

    This register is available only on ePWM instances that include the high-resolution extension (HRPWM). On ePWM modules that do not include the HRPWM, this location is reserved. This register is described in the TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (SPRU924). See the device specific data manual to determine which ePWM instances include this feature.

  • Page 25: Calculating Pwm Period And Frequency

    www.ti.com Signal Description EPWMxSYNCI Time-base synchronization input. Input pulse used to synchronize the time-base counter with the counter of ePWM module earlier in the synchronization chain. An ePWM peripheral can be configured to use or ignore this signal. For the first ePWM module (EPWM1) this signal comes from a device pin.

  • Page 26: Time-Base Frequency And Period

    Time-Base (TB) Submodule Figure 2-3. Time-Base Frequency and Period CTR_dir 2.2.3.1 Time-Base Period Shadow Register The time-base period register (TBPRD) has a shadow register. Shadowing allows the register update to be synchronized with the hardware. The following definitions are used to describe all shadow registers in the ePWM module: Active Register The active register controls the hardware and is responsible for actions that the hardware causes or...

  • Page 27: Time-Base Counter Synchronization Scheme 1

    www.ti.com 2.2.3.2 Time-Base Counter Synchronization A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The input synchronization for the first instance (ePWM1) comes from an external pin. The possible synchronization connections for the remaining ePWM modules are shown in Figure 2-6.

  • Page 28: Time-Base Counter Synchronization Scheme 2

    Time-Base (TB) Submodule Scheme 2 shown in Figure 2-5 A-channel only mode (GPAMCFG[EPWMMODE] = 3). If the 2804x ePWM pinout is configured for 280x compatible mode (GPAMCFG[EPWMMODE] = 0), then Scheme 1 is used. Figure 2-5. Time-Base Counter Synchronization Scheme 2 SYNCI eCAP1 EPWM13SYNCI...

  • Page 29: Time-Base Counter Synchronization Scheme 3

    www.ti.com Figure 2-6. Time-Base Counter Synchronization Scheme 3 SYNCI eCAP1 Each ePWM module can be configured to use or ignore the synchronization input. If the TBCTL[PHSEN] bit is set, then the time-base counter (TBCTR) of the ePWM module will be automatically loaded with the phase register (TBPHS) contents when one of the following conditions occur: EPWMxSYNCI: Synchronization Input Pulse: The value of the phase register is loaded into the counter register when an input synchronization pulse...

  • Page 30: Phase Locking The Time-Base Clocks Of Multiple Epwm Modules

    Time-Base (TB) Submodule 2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM modules on a device. This bit is part of the DSPs clock enable registers and is described in the specific device version of the System Control and Interrupts Reference Guide listed in TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped (default).

  • Page 31: Time-Base Down-Count Mode Waveforms

    www.ti.com Figure 2-8. Time-Base Down-Count Mode Waveforms TBCTR[15:0] 0xFFFF TBPRD (value) TBPHS (value) 0x000 EPWMxSYNCI CTR_dir CTR = zero CTR = PRD CNT_max Figure 2-9. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization TBCNT[15:0] 0xFFFF TBPRD (value) TBPHS (value) 0x0000 EPWMxSYNCI...

  • Page 32: Counter-Compare (Cc) Submodule

    Counter-Compare (CC) Submodule Figure 2-10. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization TBCNT[15:0] 0xFFFF TBPRD (value) TBPHS (value) 0x0000 EPWMxSYNCI CTR_dir CTR = zero CTR = PRD CNT_max Counter-Compare (CC) Submodule Figure 2-11 illustrates the counter-compare submodule within the ePWM. Figure 2-11.

  • Page 33: Purpose Of The Counter-Compare Submodule

    This register is available only on ePWM modules with the high-resolution extension (HRPWM). On ePWM modules that do not include the HRPWM this location is reserved. This register is described in the TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (SPRU924). Refer to the device specific data manual to determine which ePWM instances include this feature.

  • Page 34: Operational Highlights For The Counter-Compare Submodule

    Counter-Compare (CC) Submodule The key signals associated with the counter-compare submodule are described in Table 2-5. Counter-Compare Submodule Key Signals Signal Description of Event CTR = CMPA Time-base counter equal to the active counter-compare A value CTR = CMPB Time-base counter equal to the active counter-compare B value CTR = PRD Time-base counter equal to the active period.

  • Page 35: Counter-Compare Event Waveforms In Up-Count Mode

    www.ti.com Up-down-count mode: used to generate a symmetrical PWM waveform. To best illustrate the operation of the first three modes, the timing diagrams in Figure 2-16 show when events are generated and how the EPWMxSYNCI signal interacts. Figure 2-13. Counter-Compare Event Waveforms in Up-Count Mode TBCTR[15:0] 0xFFFF TBPRD...

  • Page 36: Counter-Compare Events In Up-Down-Count Mode, Tbctl[Phsdir = 0] Count Down On Synchronization Event

    Counter-Compare (CC) Submodule Figure 2-15. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On TBCTR[15:0] 0xFFFF TBPRD (value) CMPA (value) CMPB (value) TBPHS (value) 0x0000 EPWMxSYNCI CTR = CMPB CTR = CMPA Figure 2-16. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On TBCTR[15:0] 0xFFFF TBPRD...

  • Page 37: Action-Qualifier (Aq) Submodule

    www.ti.com Action-Qualifier (AQ) Submodule Figure 2-17 shows the action-qualifier (AQ) submodule (see shaded block) in the ePWM system. EPWMxSYNCI CTR = PRD Time-Base EPWMxSYNCO (TB) CTR = CMPA Counter Compare CTR = CMPB (CC) The action-qualifier submodule has the most important role in waveform construction and PWM generation.

  • Page 38: Action-Qualifier Submodule Inputs And Outputs

    Action-Qualifier (AQ) Submodule The action-qualifier submodule is based on event-driven logic. It can be thought of as a programmable cross switch with events at the input and actions at the output, all of which are software controlled via the set of registers shown in Table Figure 2-18.

  • Page 39: Possible Action-Qualifier Actions For Epwmxa And Epwmxb Outputs

    www.ti.com Actions are specified independently for either output (EPWMxA or EPWMxB). Any or all events can be configured to generate actions on a given output. For example, both CTR = CMPA and CTR = CMPB can operate on output EPWMxA. All qualifier actions are configured via the control registers found at the end of this section.

  • Page 40: Action-Qualifier Event Priority

    Action-Qualifier (AQ) Submodule 2.4.3 Action-Qualifier Event Priority It is possible for the ePWM action qualifier to receive more than one event at the same time. In this case events are assigned a priority by the hardware. The general rule is events occurring later in time have a higher priority and software forced events always have the highest priority.

  • Page 41: Waveforms For Common Configurations

    www.ti.com Table 2-11. Behavior if CMPA/CMPB is Greater than the Period Counter Mode Compare on Up-Count Event CAU/CBU Up-Count Mode If CMPA/CMPB occurs on a compare match (TBCTR=CMPA or CMPB). If CMPA/CMPB > TBPRD, then the event will not occur. Down-Count Mode Never occurs.

  • Page 42: Up-Down-Count Mode Symmetrical Waveform

    Action-Qualifier (AQ) Submodule When using this configuration in practice, if you load CMPA/CMPB on zero, then use CMPA/CMPB values greater than or equal to 1. If you load CMPA/CMPB on period, then use CMPA/CMPB values less than or equal to TBPRD-1. This means there will always be a pulse of at least one TBCLK cycle in a PWM period which, when very short, tend to be ignored by the system.

  • Page 43: Up, Single Edge Asymmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb-Active High

    www.ti.com Figure 2-21. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and TBCTR TBPRD value EPWMxA EPWMxB PWM period = (TBPRD + 1 ) Duty modulation for EPWMxA is set by CMPA, and is active high (that is, high time duty proportional to CMPA). Duty modulation for EPWMxB is set by CMPB and is active high (that is, high time duty proportional to CMPB).

  • Page 44: Up, Single Edge Asymmetric Waveform With Independent Modulation On Epwmxa And Epwmxb-Active Low

    Action-Qualifier (AQ) Submodule Figure 2-22. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and TBCTR TBPRD value EPWMxA EPWMxB PWM period = (TBPRD + 1 ) Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to CMPA). Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB).

  • Page 45: Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation On Epwmxa

    www.ti.com Example 2-3. Code Sample for // Initialization Time // = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.TBPRD = 600; EPwm1Regs.CMPA.half.CMPA = 350; EPwm1Regs.CMPB = 200; EPwm1Regs.TBPHS = 0;...
  • Page 46 Action-Qualifier (AQ) Submodule Example 2-4. Code Sample for // Initialization Time // = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.TBPRD = 600; EPwm1Regs.CMPA.half.CMPA = 200; EPwm1Regs.CMPB = 400;...

  • Page 47: Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb - Active Low

    www.ti.com Figure 2-24. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on TBCTR TBPRD value EPWMxA EPWMxB PWM period = 2 x TBPRD TBCLK Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to CMPA). Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB).

  • Page 48: Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation On Epwmxa And

    Action-Qualifier (AQ) Submodule Figure 2-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB — Complementary TBCTR TBPRD value EPWMxA EPWMxB PWM period = 2 TBPRD TBCLK Duty modulation for EPWMxA is set by CMPA, and is active low, i.e., low time duty proportional to CMPA Duty modulation for EPWMxB is set by CMPB and is active high, i.e., high time duty proportional to CMPB Outputs EPWMx can drive upper/lower (complementary) power switches Dead-band = CMPB - CMPA (fully programmable edge placement by software).

  • Page 49: Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation On Epwmxa-Active Low

    www.ti.com Figure 2-26. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on TBCTR EPWMxA EPWMxB PWM period = 2 TBPRD TBCLK Rising edge and falling edge can be asymmetrically positioned within a PWM cycle. This allows for pulse placement techniques. Duty modulation for EPWMxA is set by CMPA and CMPB.

  • Page 50: Dead-Band Generator (Db) Submodule

    Dead-Band Generator (DB) Submodule Dead-Band Generator (DB) Submodule Figure 2-27 illustrates the dead-band submodule within the ePWM module. EPWMxSYNCI CTR = PRD Time-Base EPWMxSYNCO (TB) CTR = CMPA Counter Compare CTR = CMPB (CC) 2.5.1 Purpose of the Dead-Band Submodule The "Action-qualifier (AQ) Module"...

  • Page 51: Operational Highlights For The Dead-Band Submodule

    www.ti.com 2.5.3 Operational Highlights for the Dead-Band Submodule The following sections provide the operational highlights. The dead-band submodule has two groups of independent selection options as shown in Input Source Selection: The input signals to the dead-band module are the EPWMxA and EPWMxB output signals from the action-qualifier.

  • Page 52: Classical Dead-Band Operating Modes

    Dead-Band Generator (DB) Submodule action-qualifier submodule to generate the signal as shown for EPWMxA. Mode 6: Bypass rising-edge-delay and Mode 7: Bypass falling-edge-delay Finally the last two entries in or rising-edge-delay (RED) blocks are bypassed. Table 2-13. Classical Dead-Band Operating Modes Mode EPWMxA and EPWMxB Passed Through (No Delay) Active High Complementary (AHC)

  • Page 53: Dead-Band Waveforms For Typical Cases (0% < Duty < 100%)

    www.ti.com Figure 2-29 shows waveforms for typical cases where 0% < duty < 100%. Figure 2-29. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) Original (outA) Rising Edge Delayed (RED) Falling Edge Delayed (FED) Active High Complementary (AHC) Active Low Complementary (ALC)

  • Page 54: Dead-Band Delay Values In Μs As A Function Of Dbfed And Dbred

    Dead-Band Generator (DB) Submodule The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED) delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit registers and their value represents the number of time-base clock, TBCLK, periods a signal edge is delayed by.

  • Page 55: Pwm-Chopper (Pc) Submodule

    www.ti.com PWM-Chopper (PC) Submodule Figure 2-30 illustrates the PWM-chopper (PC) submodule within the ePWM module. EPWMxSYNCI CTR = PRD Time-Base EPWMxSYNCO (TB) CTR = CMPA Counter Compare CTR = CMPB (CC) The PWM-chopper submodule allows a high-frequency carrier signal to modulate the PWM waveform generated by the action-qualifier and dead-band submodules.

  • Page 56: Waveforms

    PWM-Chopper (PC) Submodule Figure 2-31. PWM-Chopper Submodule Operational Details EPWMxA SYSCLKOUT EPWMxB 2.6.4 Waveforms Figure 2-32 shows simplified waveforms of the chopping action only; one-shot and duty-cycle control are not shown. Details of the one-shot and duty-cycle control are discussed in the following sections. Figure 2-32.

  • Page 57: Pwm-Chopper Submodule Waveforms Showing The First Pulse And Subsequent Sustaining Pulses

    www.ti.com 2.6.4.1 One-Shot Pulse The width of the first pulse can be programmed to any of 16 possible pulse width values. The width or period of the first pulse is given by: 1stpulse SYSCLKOUT Where T is the period of the system clock (SYSCLKOUT) and OSHTWTH is the four control bits SYSCLKOUT (value from 1 to 16) Figure 2-33...

  • Page 58: Pwm-Chopper Submodule Waveforms Showing The Pulse Width (Duty Cycle) Control Of Sustaining Pulses

    PWM-Chopper (PC) Submodule 2.6.4.2 Duty Cycle Control Pulse transformer-based gate drive designs need to comprehend the magnetic properties or characteristics of the transformer and associated circuitry. Saturation is one such consideration. To assist the gate drive designer, the duty cycles of the second and subsequent pulses have been made programmable.

  • Page 59: Trip-Zone (Tz) Submodule

    www.ti.com Trip-Zone (TZ) Submodule Figure 2-35 shows how the trip-zone (TZ) submodule fits within the ePWM module. EPWMxSYNCI CTR = PRD Time-Base EPWMxSYNCO (TB) CTR = CMPA Counter Compare CTR = CMPB (CC) Each ePWM module is connected to six TZn signals (TZ1 to TZ6) that are sourced from the GPIO MUX. These signals indicate external fault or trip conditions, and the ePWM outputs can be programmed to respond accordingly when faults occur.

  • Page 60: Controlling And Monitoring The Trip-Zone Submodule

    Trip-Zone (TZ) Submodule 2.7.2 Controlling and Monitoring the Trip-Zone Submodule The trip-zone submodule operation is controlled and monitored through the following registers: Register Name Address offset TZSEL 0x0012 reserved 0x0013 TZCTL 0x0014 TZEINT 0x0015 TZFLG 0x0016 TZCLR 0x0017 TZFRC 0x0018 All trip-zone registers are EALLOW protected and can be modified only after executing the EALLOW instruction.

  • Page 61: Possible Actions On A Trip Event

    www.ti.com Table 2-18. Possible Actions On a Trip Event TZCTL[TZA] and/or TZCTL[TZB] Example 2-8. Trip-Zone Configurations Scenario A: A one-shot trip event on TZ1 pulls both EPWM1A, EPWM1B low and also forces EPWM2A and EPWM2B high. Configure the ePWM1 registers as follows: –...

  • Page 62: Generating Trip Event Interrupts

    Trip-Zone (TZ) Submodule 2.7.4 Generating Trip Event Interrupts Figure 2-36 Figure 2-37 Figure 2-36. Trip-Zone Submodule Mode Control Logic EPWMxA EPWMxB CTR=zero TZFRC[CBC] TZSEL[CBC1 to CBC6] TZCLR[OST] TZFRC[OSHT] TZSEL[OSHT1 to OSHT6] ePWM Submodules illustrate the trip-zone submodule control and interrupt logic, respectively. TZCTL[TZB] TZCTL[TZA] Clear...

  • Page 63: Event-Trigger (Et) Submodule

    www.ti.com Figure 2-37. Trip-Zone Submodule Interrupt Logic TZCLR[INT] Clear Generate EPWMx_TZINT interrupt pulse when (PIE) input=1 Event-Trigger (ET) Submodule The key functions of the event-trigger submodule are: Receives event inputs generated by the time-base and counter-compare submodules Uses the time-base direction information for up/down event qualification Uses prescaling logic to issue interrupt requests and ADC start of conversion at: –...

  • Page 64: Operational Overview Of The Event-Trigger Submodule

    Event-Trigger (ET) Submodule 2.8.1 Operational Overview of the Event-Trigger Submodule The following sections describe the event-trigger submodule's operational highlights. Each ePWM module has one interrupt request line connected to the PIE and two start of conversion signals (one for each sequencer) connected to the ADC module. As shown in conversion for all ePWM modules are ORed together and hence multiple modules can initiate an ADC start of conversion.

  • Page 65: Event-Trigger Submodule Showing Event Inputs And Prescaled Outputs

    www.ti.com Figure 2-40. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs CTR=Zero CTR=PRD CTR=CMPA Direction qualifier CTR=CMPB CTR_dir The key registers used to configure the event-trigger submodule are shown in Table 2-19. Event-Trigger Submodule Registers Register Name Address offset ETSEL 0x0019 ETPS 0x001A...

  • Page 66: Event-Trigger Interrupt Generator

    Event-Trigger (ET) Submodule The number of events that have occurred can be read from the interrupt event counter (ETPS[INTCNT]) register bits. That is, when the specified event occurs the ETPS[INTCNT] bits are incremented until they reach the value specified by ETPS[INTPRD]. When ETPS[INTCNT] = ETPS[INTPRD] the counter stops counting and its output is set.

  • Page 67: Event-Trigger Soca Pulse Generator

    www.ti.com Figure 2-42. Event-Trigger SOCA Pulse Generator ETCLR[SOCA] Clear Generate SOCA input = 1 Figure 2-43 shows the operation of the event-trigger's start-of-conversion-B (SOCB) pulse generator. The event-trigger's SOCB pulse generator operates the same way as the SOCA. Figure 2-43. Event-Trigger SOCB Pulse Generator ETCLR[SOCB] Generate SOCB...
  • Page 68 ePWM Submodules SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback...

  • Page 69: Applications To Power Topologies

    An ePWM module has all the local resources necessary to operate completely as a standalone module or to operate in synchronization with other identical ePWM modules. Topic Overview of Multiple Modules Key Configuration Capabilities Controlling Multiple Buck Converters With Independent Frequencies Controlling Multiple Buck Converters With Same Frequencies Controlling Multiple Half H-Bridge (HHB) Converters...

  • Page 70: Overview Of Multiple Modules

    Overview of Multiple Modules Overview of Multiple Modules Previously in this user's guide, all discussions have described the operation of a single module. To facilitate the understanding of multiple modules working together in a system, the ePWM module described in reference is represented by the more simplified block diagram shown in simplified ePWM block shows only the key resources needed to explain how a multiswitch power topology is controlled with multiple ePWM modules working together.

  • Page 71: Controlling Multiple Buck Converters With Independent Frequencies

    www.ti.com Figure 3-2. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave Ext SyncIn (optional) Master SyncIn Phase reg CTR=0 CTR=CMPB SyncOut Controlling Multiple Buck Converters With Independent Frequencies One of the simplest power converter topologies is the buck. A single ePWM module configured as a master can control two buck stages with the same PWM frequency.

  • Page 72: Control Of Four Buck Stages. Here F

    Controlling Multiple Buck Converters With Independent Frequencies Figure 3-3. Control of Four Buck Stages. Here F Master1 Phase reg SyncIn CTR=zero CTR=CMPB SyncOut Master2 Phase reg SyncIn CTR=zero CTR=CMPB SyncOut Master3 Phase reg SyncIn CTR=zero CTR=CMPB SyncOut Master4 Phase reg SyncIn CTR=zero CTR=CMPB...

  • Page 73: Buck Waveforms For Figure 3-3 (Note: Only Three Bucks Shown Here)

    www.ti.com Figure 3-4. Buck Waveforms for EPWM1A EPWM2A EPWM3A Indicates this event triggers an interrupt SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback Controlling Multiple Buck Converters With Independent Frequencies Figure 3-3 (Note: Only three bucks shown here) 1200 Pulse center 1150...
  • Page 74 Controlling Multiple Buck Converters With Independent Frequencies Example 3-1. Configuration for Example in //===================================================================== (Note: code for only 3 modules shown) // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 1200; EPwm1Regs.TBPHS = 0; EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;...

  • Page 75: Controlling Multiple Buck Converters With Same Frequencies

    www.ti.com Controlling Multiple Buck Converters With Same Frequencies If synchronization is a requirement, ePWM module 2 can be configured as a slave and can operate at integer multiple (N) frequencies of module 1. The sync signal from master to slave ensures these modules remain locked.

  • Page 76: Buck Waveforms For Figure

    Controlling Multiple Buck Converters With Same Frequencies Figure 3-6. Buck Waveforms for EPWM1A EPWM1B EPWM2A EPWM2B Applications to Power Topologies Figure 3-5 (Note: F SPRU791D – November 2004 – Revised October 2007 www.ti.com PWM2 PWM1) Submit Documentation Feedback...
  • Page 77 www.ti.com Example 3-2. Code Snippet for Configuration in //===================================================================== // Config //===================================================================== // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 600; EPwm1Regs.TBPHS = 0; EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;...

  • Page 78: Controlling Multiple Half H-Bridge (Hhb) Converters

    Controlling Multiple Half H-Bridge (HHB) Converters Controlling Multiple Half H-Bridge (HHB) Converters Topologies that require control of multiple switching elements can also be addressed with these same ePWM modules. It is possible to control a Half-H bridge stage with a single ePWM module. This control can be extended to multiple stages.

  • Page 79: Fpwm1

    www.ti.com Figure 3-8. Half-H Bridge Waveforms for EPWM1A EPWM1B EPWM2A EPWM2B SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback Controlling Multiple Half H-Bridge (HHB) Converters Figure 3-7 (Note: Here F Pulse Center Pulse Center PWM2 PWM1 Applications to Power Topologies...

  • Page 80: Controlling Dual 3-Phase Inverters For Motors (Aci And Pmsm)

    Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) Example 3-3. Code Snippet for Configuration in //===================================================================== // Config //===================================================================== // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 600; EPwm1Regs.TBPHS = 0; EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;...

  • Page 81: Control Of Dual 3-Phase Inverter Stages As Is Commonly Used In Motor Control

    www.ti.com Figure 3-9. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control Ext SyncIn (optional) Master Phase reg SyncIn CTR=zero CTR=CMPB SyncOut Slave Phase reg SyncIn CTR=zero CTR=CMPB SyncOut Slave Phase reg SyncIn CTR=zero CTR=CMPB SyncOut Slave Phase reg SyncIn...

  • Page 82: 3-Phase Inverter Waveforms For Figure 3-9 (Only One Inverter Shown)

    Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) Figure 3-10. 3-Phase Inverter Waveforms for EPWM1A EPWM1B EPWM2A EPWM2B EPWM3A EPWM3B Applications to Power Topologies Figure 3-9 SPRU791D – November 2004 – Revised October 2007 www.ti.com (Only One Inverter Shown) Submit Documentation Feedback...
  • Page 83 www.ti.com Example 3-4. Code Snippet for Configuration in //===================================================================== // Configuration //===================================================================== // Initialization Time //========================// EPWM Module 1 config EPwm1Regs.TBPRD = 800; EPwm1Regs.TBPHS = 0; EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Symmetrical mode EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;...

  • Page 84: Practical Applications Using Phase Control Between Pwm Modules

    Practical Applications Using Phase Control Between PWM Modules Practical Applications Using Phase Control Between PWM Modules So far, none of the examples have made use of the phase register (TBPHS). It has either been set to zero or its value has been a don't care. However, by programming appropriate values into TBPHS, multiple PWM modules can address another class of power topologies that rely on phase relationship between legs (or stages) for correct operation.

  • Page 85: Controlling A 3-Phase Interleaved Dc/Dc Converter

    www.ti.com Figure 3-12. Timing Waveforms Associated With Phase Control Between 2 Modules TBCTR[0-15] FFFFh Master Module TBPRD 0000 CTR = PRD (SycnOut) TBCTR[0-15] FFFFh Slave Module TBPRD TBPHS 0000 SyncIn Controlling a 3-Phase Interleaved DC/DC Converter A popular power topology that makes use of phase-offset between modules is shown in system uses three PWM modules, with module 1 configured as the master.

  • Page 86: Control Of A 3-Phase Interleaved Dc/Dc Converter

    Controlling a 3-Phase Interleaved DC/DC Converter Figure 3-13. Control of a 3-Phase Interleaved DC/DC Converter Ext SyncIn (optional) Master Phase reg SyncIn CTR=zero CTR=CMPB SyncOut Slave Phase reg SyncIn =120 =120 CTR=zero CTR=CMPB SyncOut Slave Phase reg SyncIn =240 CTR=zero CTR=CMPB SyncOut Applications to Power Topologies...

  • Page 87: 3-Phase Interleaved Dc/Dc Converter Waveforms For Figure 3-13

    www.ti.com Figure 3-14. 3-Phase Interleaved DC/DC Converter Waveforms for EPWM1A EPWM1B 2=120 TBPHS (=300) EPWM2A EPWM2B TBPHS (=300) EPWM3A EPWM3B SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback Controlling a 3-Phase Interleaved DC/DC Converter 2=120 Figure 3-13 Applications to Power Topologies...
  • Page 88 Controlling a 3-Phase Interleaved DC/DC Converter Example 3-5. Code Snippet for Configuration in //===================================================================== // Config // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 450; EPwm1Regs.TBPHS = 0; EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;...

  • Page 89: Controlling Zero Voltage Switched Full Bridge (Zvsfb) Converter

    www.ti.com Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter The example given in Figure 3-15 (modules). In such a case, control is achieved by modulating the duty cycle. It is also possible to dynamically change the phase value on a cycle-by-cycle basis. This feature lends itself to controlling a class of power topologies known as phase-shifted full bridge, or zero voltage switched full bridge.

  • Page 90: Zvs Full-H Bridge Waveforms

    Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter Figure 3-16. ZVS Full-H Bridge Waveforms É É É É É É É É É EPWM1A É É É É É É Power phase EPWM1B TBPHS =(1200− 2) É É É EPWM2A É...
  • Page 91 www.ti.com Example 3-6. Code Snippet for Configuration in //===================================================================== // Config //===================================================================== // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 1200; EPwm1Regs.CMPA = 600; EPwm1Regs.TBPHS = 0; EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;...
  • Page 92 Applications to Power Topologies SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback...

  • Page 93: Spru791D - November 2004 - Revised October 2007

    This chapter includes the register layouts and bit description for the submodules. Topic Time-Base Submodule Registers Counter-Compare Submodule Registers Action-Qualifier Submodule Registers Dead-Band Submodule Registers PWM-Chopper Submodule Control Register Trip-Zone Submodule Control and Status Registers Event-Trigger Submodule Registers Proper Interrupt Initialization Procedure SPRU791D –...

  • Page 94: Time-Base Submodule Registers

    Time-Base Submodule Registers Time-Base Submodule Registers Figure 4-1 through Figure 4-5 Figure 4-1. Time-Base Period Register (TBPRD) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-1. Time-Base Period Register (TBPRD) Field Descriptions Bits Name Value Description 15-0...

  • Page 95: Time-Base Control Register (Tbctl)

    www.ti.com Figure 4-4. Time-Base Control Register (TBCTL) FREE, SOFT PHSDIR R/W-0 R/W-0 HSPCLKDIV SWFSYNC R/W-0,0,1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-4. Time-Base Control Register (TBCTL) Field Descriptions Field Value Description 15:14 FREE, SOFT Emulation Mode Bits.
  • Page 96 Time-Base Submodule Registers Table 4-4. Time-Base Control Register (TBCTL) Field Descriptions (continued) Field Value Description SWFSYNC Software Forced Synchronization Pulse Writing a 0 has no effect and reads always return a 0. Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module.

  • Page 97: Counter-Compare Submodule Registers

    www.ti.com Reserved LEGEND: R/W = Read/Write; R = Read only; R/W1C = Read/Write 1 to clear; -n = value after reset Table 4-5. Time-Base Status Register (TBSTS) Field Descriptions Field Value Description 15:3 Reserved Reserved CTRMAX Time-Base Counter Max Latched Status Bit Reading a 0 indicates the time-base counter never reached its maximum value.

  • Page 98: Counter-Compare B Register (Cmpb)

    Counter-Compare Submodule Registers Table 4-6. Counter-Compare A Register (CMPA) Field Descriptions Bits Name Description 15-0 CMPA The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a "time-base counter equal to counter compare A"...

  • Page 99: Action-Qualifier Submodule Registers

    www.ti.com Figure 4-8. Counter-Compare Control Register (CMPCTL) Reserved SHDWBMODE Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-8. Counter-Compare Control Register (CMPCTL) Field Descriptions Bits Name Value 15-10 Reserved SHDWBFULL SHDWAFULL Reserved SHDWBMODE Reserved SHDWAMODE...

  • Page 100: Action-Qualifier Output A Control Register (Aqctla)

    Action-Qualifier Submodule Registers Figure 4-9. Action-Qualifier Output A Control Register (AQCTLA) Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-9. Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions Bits Name Value Description 15-12 Reserved Reserved...

  • Page 101: Action-Qualifier Output B Control Register (Aqctlb)

    www.ti.com Figure 4-10. Action-Qualifier Output B Control Register (AQCTLB) Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-10. Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions Bits Name Value Description 15-12 Reserved 11-10 Action when the counter equals the active CMPB register and the counter is decrementing.

  • Page 102: Action-Qualifier Software Force Register (Aqsfrc)

    Action-Qualifier Submodule Registers Figure 4-11. Action-Qualifier Software Force Register (AQSFRC) RLDCSF OTSFB R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-11. Action-Qualifier Software Force Register (AQSFRC) Field Descriptions Field Value Description 15:8 Reserved RLDCSF AQCSFRC Active Register Reload From Shadow Options...

  • Page 103: Dead-Band Submodule Registers

    www.ti.com Table 4-12. Action-qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions Bits Name Value Description 15-4 Reserved Reserved CSFB Continuous Software Force on Output B In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register.

  • Page 104: Dead-Band Generator Control Register (Dbctl) Field Descriptions

    Dead-Band Submodule Registers Table 4-13. Dead-Band Generator Control Register (DBCTL) Field Descriptions Bits Name Value 15-6 Reserved IN_MODE POLSEL OUT_MODE Registers Description Reserved Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in This allows you to select the input source to the falling-edge and rising-edge delay.

  • Page 105: Pwm-Chopper Submodule Control Register

    www.ti.com Figure 4-14. Dead-Band Generator Rising Edge Delay Register (DBRED) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-14. Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions Bits Name Value Description 15-10 Reserved Reserved Rising Edge Delay Count.

  • Page 106: Trip-Zone Submodule Control And Status Registers

    Trip-Zone Submodule Control and Status Registers Table 4-16. PWM-Chopper Control Register (PCCTL) Bit Descriptions (continued) Bits Name Value 10-8 CHPDUTY CHPFREQ OSHTWTH 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CHPEN Trip-Zone Submodule Control and Status Registers Figure 4-17 Table 4-17 Registers...

  • Page 107: Trip-Zone Select Register (Tzsel)

    www.ti.com Reserved OSHT6 R/W-0 Reserved CBC6 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-17. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions Bits Name Value One-Shot (OSHT) Trip-zone enable/disable. When any of the enabled pins go low, a one-shot trip event occurs for this ePWM module.

  • Page 108: Trip-Zone Control Register (Tzctl)

    Trip-Zone Submodule Control and Status Registers Table 4-17. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions (continued) Bits Name Value CBC2 CBC1 Figure 4-18. Trip-Zone Control Register (TZCTL) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-18.

  • Page 109: Trip-Zone Flag Register (Tzflg)

    www.ti.com Table 4-19. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions (continued) Bits Name Value Description Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT PIE interrupt. Trip-zone Cycle-by-Cycle Interrupt Enable Disable cycle-by-cycle interrupt generation. Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt.

  • Page 110: Event-Trigger Submodule Registers

    Event-Trigger Submodule Registers Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-21. Trip-Zone Clear Register (TZCLR) Field Descriptions Bits Name Value 15-3 Reserved Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-22.

  • Page 111: Event-Trigger Selection Register (Etsel)

    www.ti.com Figure 4-23. Event-Trigger Selection Register (ETSEL) SOCBEN SOCBSEL R/W-0 R/W-0 Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-23. Event-Trigger Selection Register (ETSEL) Field Descriptions Bits Name Value SOCBEN 14-12 SOCBSEL SOCAEN 10-8 SOCASEL Reserved...

  • Page 112: Event-Trigger Prescale Register (Etps)

    Event-Trigger Submodule Registers Table 4-23. Event-Trigger Selection Register (ETSEL) Field Descriptions (continued) Bits Name Value INTSEL Figure 4-24. Event-Trigger Prescale Register (ETPS) SOCBCNT Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-24. Event-Trigger Prescale Register (ETPS) Field Descriptions Bits Name 15-14...

  • Page 113: Event-Trigger Flag Register (Etflg)

    www.ti.com Table 4-24. Event-Trigger Prescale Register (ETPS) Field Descriptions (continued) Bits Name SOCAPRD Reserved INTCNT INTPRD Figure 4-25. Event-Trigger Flag Register (ETFLG) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback Description ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select...

  • Page 114: Event-Trigger Clear Register (Etclr)

    Event-Trigger Submodule Registers Table 4-25. Event-Trigger Flag Register (ETFLG) Field Descriptions Bits Name Value 15-4 Reserved SOCB SOCA Reserved Figure 4-26. Event-Trigger Clear Register (ETCLR) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-26. Event-Trigger Clear Register (ETCLR) Field Descriptions Bits Name Value...

  • Page 115: Proper Interrupt Initialization Procedure

    www.ti.com Proper Interrupt Initialization Procedure When the ePWM peripheral clock is enabled it may be possible that interrupt flags may be set due to spurious events due to the ePWM registers not being properly initialized. The proper procedure for initializing the ePWM peripheral is as follows: 1.
  • Page 116 Registers SPRU791D – November 2004 – Revised October 2007 Submit Documentation Feedback...

  • Page 117: A Revision History

    This document was revised to SPRU791D from SPRU791C. The scope of the revision was limited to technical changes as shown in Location Modifications, Additions, and Deletions Figure 2-12 Modified the Detailed View of the Counter-compare Submodule figure Section 2.2.3 Corrected register name from TBCTRL to TBCTL in the second paragraph of calculating PWM Period and Frequency Figure 2-2 Modified figure...
  • Page 118 Appendix A Location Modifications, Additions, and Deletions Table 4-13 Modified the "10" description of the Dead-Band Generator Control Register OUT_MODE field. Table 4-14 Modified the bit numbers of the Dead-Band Generator Rising Edge Delay Register Reserved field Table 4-15 Modified the bit numbers of the Dead-Band Generator Falling Edge Delay Register Reserved field Section 2.8.1 Updated description of event counter Table 4-24...

  • Page 119: Important Notice

    TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers amplifier.ti.com...

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