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Texas Instruments 28xxx manual available for free PDF download: Reference Manual
Texas Instruments 28xxx Reference Manual (119 pages)
Texas Instruments Enhanced Pulse Width Modulator (ePWM) Reference Guide
Brand:
Texas Instruments
| Category:
Accessories
| Size: 1 MB
Table of Contents
Table of Contents
3
Preface
9
Read this First
9
Related Documentation from Texas Instruments
9
1 Introduction
13
Introduction
14
Submodule Overview
14
Multiple Epwm Modules
15
Submodules and Signal Connections for an Epwm Module
16
Register Mapping
17
Epwm Submodules and Critical Internal Signal Interconnects
17
Epwm Module Control and Status Register Set Grouped by Submodule
18
2 Epwm Submodules
19
Overview
20
Submodule Configuration Parameters
20
Time-Base (TB) Submodule
23
Purpose of the Time-Base Submodule
23
Time-Base Submodule Block Diagram
23
Controlling and Monitoring the Time-Base Submodule
24
Time-Base Submodule Signals and Registers
24
Time-Base Submodule Registers
24
Calculating PWM Period and Frequency
25
Key Time-Base Signals
25
Time-Base Frequency and Period
26
Time-Base Counter Synchronization Scheme 1
27
Time-Base Counter Synchronization Scheme 2
28
Time-Base Counter Synchronization Scheme 3
29
Phase Locking the Time-Base Clocks of Multiple Epwm Modules
30
Time-Base Counter Modes and Timing Waveforms
30
Time-Base Up-Count Mode Waveforms
30
Time-Base Down-Count Mode Waveforms
31
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count down on Synchronization Event
31
Counter-Compare (CC) Submodule
32
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count up on Synchronization Event
32
Counter-Compare Submodule
32
Purpose of the Counter-Compare Submodule
33
Controlling and Monitoring the Counter-Compare Submodule
33
Detailed View of the Counter-Compare Submodule
33
Counter-Compare Submodule Registers
33
Operational Highlights for the Counter-Compare Submodule
34
Count Mode Timing Waveforms
34
Counter-Compare Submodule Key Signals
34
Counter-Compare Event Waveforms in Up-Count Mode
35
Counter-Compare Events in Down-Count Mode
35
Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count down on Synchronization Event
36
Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count up on Synchronization Event
36
Action-Qualifier (AQ) Submodule
37
Purpose of the Action-Qualifier Submodule
37
Action-Qualifier Submodule Control and Status Register Definitions
37
Action-Qualifier Submodule
37
Action-Qualifier Submodule Registers
37
Action-Qualifier Submodule Inputs and Outputs
38
Action-Qualifier Submodule Possible Input Events
38
Possible Action-Qualifier Actions for Epwmxa and Epwmxb Outputs
39
Action-Qualifier Event Priority
40
Action-Qualifier Event Priority for Up-Down-Count Mode
40
Action-Qualifier Event Priority for Up-Count Mode
40
Action-Qualifier Event Priority for Down-Count Mode
40
Waveforms for Common Configurations
41
Behavior if CMPA/CMPB Is Greater than the Period
41
Up-Down-Count Mode Symmetrical Waveform
42
Up, Single Edge Asymmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb-Active High
43
Up, Single Edge Asymmetric Waveform with Independent Modulation on Epwmxa and Epwmxb-Active Low
44
Up-Count, Pulse Placement Asymmetric Waveform with Independent Modulation on Epwmxa
45
Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Active Low
47
Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and
48
Up-Down-Count, Dual Edge Asymmetric Waveform, with Independent Modulation on Epwmxa-Active Low
49
Dead-Band Generator (DB) Submodule
50
Purpose of the Dead-Band Submodule
50
Controlling and Monitoring the Dead-Band Submodule
50
Dead_Band Submodule
50
Dead-Band Generator Submodule Registers
50
Operational Highlights for the Dead-Band Submodule
51
Configuration Options for the Dead-Band Submodule
51
Classical Dead-Band Operating Modes
52
Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
53
Dead-Band Delay Values in Μs as a Function of DBFED and DBRED
54
PWM-Chopper (PC) Submodule
55
Purpose of the PWM-Chopper Submodule
55
Controlling the PWM-Chopper Submodule
55
Operational Highlights for the PWM-Chopper Submodule
55
PWM-Chopper Submodule
55
PWM-Chopper Submodule Registers
55
Waveforms
56
PWM-Chopper Submodule Operational Details
56
Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only
56
PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses
57
Possible Pulse Width Values for SYSCLKOUT = 100 Mhz
57
PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses
58
Trip-Zone (TZ) Submodule
59
Purpose of the Trip-Zone Submodule
59
Trip-Zone Submodule
59
Controlling and Monitoring the Trip-Zone Submodule
60
Operational Highlights for the Trip-Zone Submodule
60
Trip-Zone Submodule Registers
60
Possible Actions on a Trip Event
61
Generating Trip Event Interrupts
62
Trip-Zone Submodule Mode Control Logic
62
Event-Trigger (ET) Submodule
63
Trip-Zone Submodule Interrupt Logic
63
Event-Trigger Submodule
63
Operational Overview of the Event-Trigger Submodule
64
Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion and Interrupt Signals
64
Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
65
Event-Trigger Submodule Registers
65
Event-Trigger Interrupt Generator
66
Event-Trigger SOCA Pulse Generator
67
Event-Trigger SOCB Pulse Generator
67
3 Applications to Power Topologies
69
Overview of Multiple Modules
70
Key Configuration Capabilities
70
Simplified Epwm Module
70
Controlling Multiple Buck Converters with Independent Frequencies
71
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
71
Control of Four Buck Stages. here F
72
Pwm1 Fpwm2 Fpwm3 Fpwm4
72
Buck Waveforms for Figure 3-3 (Note: Only Three Bucks Shown Here)
73
Controlling Multiple Buck Converters with same Frequencies
75
Control of Four Buck Stages
75
N X FPWM1
75
Pwm2 Pwm1
75
Buck Waveforms for Figure
76
Controlling Multiple Half H-Bridge (HHB) Converters
78
Control of Two Half-H Bridge Stages
78
Pwm2 Pwm1
78
N X FPWM1
78
Fpwm1
79
Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
80
Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control
81
3-Phase Inverter Waveforms for Figure 3-9 (Only One Inverter Shown)
82
Practical Applications Using Phase Control between PWM Modules
84
Configuring Two PWM Modules for Phase Control
84
Controlling a 3-Phase Interleaved DC/DC Converter
85
Timing Waveforms Associated with Phase Control between 2 Modules
85
Control of a 3-Phase Interleaved DC/DC Converter
86
3-Phase Interleaved DC/DC Converter Waveforms for Figure 3-13
87
Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
89
Controlling a Full-H Bridge Stage
89
Pwm2 Pwm1)
89
ZVS Full-H Bridge Waveforms
90
SPRU791D - November 2004 - Revised October 2007
93
Registers
93
Time-Base Submodule Registers
94
Time-Base Period Register (TBPRD)
94
Time-Base Phase Register (TBPHS)
94
Time-Base Counter Register (TBCTR)
94
Time-Base Period Register (TBPRD) Field Descriptions
94
Time-Base Phase Register (TBPHS) Field Descriptions
94
Time-Base Counter Register (TBCTR) Field Descriptions
94
Time-Base Control Register (TBCTL)
95
Time-Base Control Register (TBCTL) Field Descriptions
95
Counter-Compare Submodule Registers
97
Time-Base Status Register (TBSTS)
97
Counter-Compare a Register (CMPA)
97
Time-Base Status Register (TBSTS) Field Descriptions
97
Counter-Compare B Register (CMPB)
98
Counter-Compare a Register (CMPA) Field Descriptions
98
Counter-Compare B Register (CMPB) Field Descriptions
98
Action-Qualifier Submodule Registers
99
Counter-Compare Control Register (CMPCTL)
99
Counter-Compare Control Register (CMPCTL) Field Descriptions
99
Action-Qualifier Output a Control Register (AQCTLA)
100
Action-Qualifier Output a Control Register (AQCTLA) Field Descriptions
100
Action-Qualifier Output B Control Register (AQCTLB)
101
Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions
101
Action-Qualifier Software Force Register (AQSFRC)
102
Action-Qualifier Continuous Software Force Register (AQCSFRC)
102
Action-Qualifier Software Force Register (AQSFRC) Field Descriptions
102
Dead-Band Submodule Registers
103
Dead-Band Generator Control Register (DBCTL)
103
Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions
103
Dead-Band Generator Control Register (DBCTL) Field Descriptions
104
PWM-Chopper Submodule Control Register
105
Dead-Band Generator Rising Edge Delay Register (DBRED)
105
Dead-Band Generator Falling Edge Delay Register (DBFED)
105
PWM-Chopper Control Register (PCCTL)
105
Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions
105
Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions
105
PWM-Chopper Control Register (PCCTL) Bit Descriptions
105
Trip-Zone Submodule Control and Status Registers
106
Trip-Zone Select Register (TZSEL)
107
Trip-Zone Submodule Select Register (TZSEL) Field Descriptions
107
Trip-Zone Control Register (TZCTL)
108
Trip-Zone Enable Interrupt Register (TZEINT)
108
Trip-Zone Control Register (TZCTL) Field Descriptions
108
Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions
108
Trip-Zone Flag Register (TZFLG)
109
Trip-Zone Flag Register (TZFLG) Field Descriptions
109
Event-Trigger Submodule Registers
110
Trip-Zone Clear Register (TZCLR)
110
Trip-Zone Force Register (TZFRC)
110
Trip-Zone Clear Register (TZCLR) Field Descriptions
110
Trip-Zone Force Register (TZFRC) Field Descriptions
110
Event-Trigger Selection Register (ETSEL)
111
Event-Trigger Selection Register (ETSEL) Field Descriptions
111
Event-Trigger Prescale Register (ETPS)
112
Event-Trigger Prescale Register (ETPS) Field Descriptions
112
Event-Trigger Flag Register (ETFLG)
113
Event-Trigger Clear Register (ETCLR)
114
Event-Trigger Flag Register (ETFLG) Field Descriptions
114
Event-Trigger Clear Register (ETCLR) Field Descriptions
114
Proper Interrupt Initialization Procedure
115
Event-Trigger Force Register (ETFRC)
115
Event-Trigger Force Register (ETFRC) Field Descriptions
115
A Revision History
117
Changes for Revision D
117
Important Notice
119
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