Evaluation module for the tas5010 digital audio pwm processor and the tas5112adfd digital audio pwm power output stage (26 pages)
Summary of Contents for Texas Instruments DAC8555EVM
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Related Documentation from Texas Instruments. Throughout this document, the acronym EVM and the phrases evaluation module and demonstration board are synonymous with the DAC8555EVM. TMS320C5000, TMS320C6000 are trademarks of Texas Instruments. LabVIEW is a trademark of National Instruments.
Overview Overview This section gives a general overview of the DAC8555EVM and describes some of the factors that must be considered when using this demonstration board. Features The DAC8555EVM is a simple evaluation module designed for a quick and easy way to evaluate the functionality and performance of the high-resolution, quad-channel, serial input DAC8555 digital-to-analog converter (DAC).
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+5V can permanently damage the DAC8555 being tested (U1). EVM Basic Functions The DAC8555EVM is designed to provide a demonstration platform for testing certain operational characteristics of the DAC8555 digital-to-analog converter. Functional evaluation of the DAC8555 can be accomplished with the use of any microprocessor, TI DSP or some sort of waveform generator.
1.3.1 Related Documentation from Texas Instruments The following documents provide information regarding Texas Instrument integrated circuits used in the assembly of the DAC8555EVM. The latest revisions of these documents are available from the TI web site http://www.ti.com. Data Sheet Literature Number...
485 and 64741. The DUT is then allowed to settle for 1ms before the meter is read. This process is repeated for all codes to generate the measurements for INL and DNL. Results of the DAC8555EVM tests are shown in Figure 9...
PCB Design and Performance Figure 9. INL and DNL Characterization Graph of DAC A SLAU204 – December 2006 DAC8555EVM User's Guide Submit Documentation Feedback...
PCB Design and Performance Figure 10. INL and DNL Characterization Graph of DAC B DAC8555EVM User's Guide SLAU204 – December 2006 Submit Documentation Feedback...
PCB Design and Performance Figure 11. INL and DNL Characterization Graph of DAC C SLAU204 – December 2006 DAC8555EVM User's Guide Submit Documentation Feedback...
PCB Design and Performance Figure 12. INL and DNL Characterization Graph of DAC D DAC8555EVM User's Guide SLAU204 – December 2006 Submit Documentation Feedback...
PCB Design and Performance Bill of Materials The parts list, showing the components used in the assembly of the DAC8555EVM, is given in Table Table 1. DAC8555EVM Parts List ITEM BOARD Ref Des PART NUMBER DESCRIPTION R11–R14 Panasonic ERJ-3GEY0R00V...
DAC channels that can be connected without colliding. Table 3 shows how the DAC output channels are mapped into the output terminal, J4, with respect to the jumper positions of JMP11, JMP12, JMP13, and JMP14. DAC8555EVM User's Guide SLAU204 – December 2006 Submit Documentation Feedback...
DAC channels when stacking two EVMs together. Output Op Amp The DAC8555EVM includes an optional signal conditioning circuit for the DAC output through an external operational amplifier, U2. The output op amp is set to unity gain configuration by default. Only one DAC output channel can be monitored at any given time.
Configures op amp U2 for a gain of 2 output without a voltage offset. JMP5 must be Close Close open. JMP6 Inverting input of op amp U2 is disconnected from the gain resistor, R9. JMP5 must be Open Open closed. DAC8555EVM User's Guide SLAU204 – December 2006 Submit Documentation Feedback...
RSTSEL pin is set high through pull-up resistor R3. RSTSEL can be driven by GPIO4, J2-14. JMP3 RSTSEL pin is set low. Indicates the corresponding pins that are shorted or closed. SLAU204 – December 2006 DAC8555EVM User's Guide Submit Documentation Feedback...
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JMP10 Negative supply rail of the op amp U2 is tied to AGND for unipolar operation. Routes V A to J4-2. JMP11 Routes V A to J4-10. DAC8555EVM User's Guide SLAU204 – December 2006 Submit Documentation Feedback...
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JMP14 Routes V D to J4-16. Routes J4-1 to U2 noninverting input. JMP15 Routes J4-3 to U2 noninverting input. Routes U2 output to J4-5. JMP16 Routes U2 output to J4-7. SLAU204 – December 2006 DAC8555EVM User's Guide Submit Documentation Feedback...
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6730 SOUTH TUCSON BLVD., TUCSON, AZ 85706 USA +5VA VCC = +15V Analog TITLE ENGINEER J. PARGUIAN DAC8555EVM VDD = +2.7V to +5.0V Digital J3A (TOP) = SAM_TSM-105-01-L-DV-P VSS = 0V to -15V Analog DRAWN BY R. BENJAMIN J3B (BOTTOM) = SAM_SSW-105-22-F-D-VS-K DOCUMENT CONTROL NO.
EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use.
TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
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