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A
B
D750
MASTER
STAND_REQ_HV_OFF
X757
X815
6
(
*
KVA)
GEN_PREP_RDY
5
(VH)
GRID_RUNNING
(AR)
4
1
0V_MPS
3
7
8
GND
2
MPS
COMMUNICATION
X811
1
2
X886
5
6
F802
1AT
X886A
5
6
BN
BU
T801
C
D
D801
0VD
RESET
*
*
6
*
5
4
1
3
0VD1
0VA
0V_MPS
7
0VD
8
+5V_MPS
0V_MPS
MPS
2
5V_MPS
~
F2
0V_MPS
V26
1AT
=
GENERATOR INTERFACE
FLOATING, GROUNDED BY GENERATOR
E
RESET
S1
RESET SW
COMP
*
RESET
*
<4.6V
+5V
RESET_HW
*
KVA
STATUSLED's
J1
12MHz
X1
AR
CPU &
PLD
FUNC.
DATA AND ADDRESS
PROM
RAM
EEPROM
128k x 8
32k x 8
RXD
TXD
ROM
+5V_MPS
0V_MPS
F
G
D801
TESTPOINTS AND LED'
s
AR
X812
KVA
COLL_ST
GRID_SP
COMP_SP
X813
V60
SPEED
FILT_P
FOCUS_P
ROT_POS
COLL_P2
V1
COLL_P1
0VD2
V60
PROM
V2
X816
V3
V1
PLD
V2
V4
V3
V4
GRID_0
ROM
TXD
CPU
J1
RXD
0VA1
7V
X814
V5
5V_REF
8k x 8
5V_DSP
I9
V6
X811
0VD1
F1
5V
V7
MPS
X815
V26
F2
0V_MPS
5V_MPS
S1
RESET SWITCH
STATUS LED'
DURING STARTUP:
s
PROM/RAM TEST V1, V4 LIT.
V2, V3 LIT IF PROM CHECKSUM ERROR.
V3, V4 LIT IF RAM ERROR.
ALL TESTS PASSED, V1-V4 ARE DARK.
V60 ~ 1HZ WHEN PLD IS PROGRAMMED
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