Table of Contents
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D+3.3VA
S D C a r d I C
t h r o u g h M B t o S D _ C N
RDSD
WRSD
CS2SD
48
1
CS2SD
CS2
BA4
A4SD
A0SD
47
2
XTST
BA3
A3SD
A1SD
46
3
XRD
BA2
RDSD
A2SD
A2SD
45
4
CS1SD
XCSI
BA1
A1SD
A3SD
44
5
WRSD
XWR
BA0
A0SD
A4SD
43
6
VDD
VSS
42
7
VSS
DT15
D15SD
41
8
R403
XI
DT14
D14SD
40
9
0/J2
VDDa
DT13
D13SD
39
10
XO
DT12
D12SD
38
11
SDCARD_CLK
CLK
DT11
D11SD
R401
0/J2
37
12
RESET
XRST
XINT
P27
R654
0/J3
36
13
XMCD
DT10
D10SD
35
14
MWP
DT9
D9SD
R402
0/J2
34
15
OCTL
DT8
D8SD
33
16
VDD
DT7
D7SD
32
17
MCLK
MCLK
DT6
D6SD
31
18
VSS
VSS
30
19
CMD
VDD
29
20
DAT0
DT5
D5SD
28
21
MCD
DAT1
DT4
D4SD
27
22
DAT2
DT3
D3SD
26
23
MWP
DAT3
DT2
D2SD
25
24
3V
DT0
DT1
D1SD
0V
CMD
DAT0
D0SD
DAT1
DAT2
DAT3
D.GND
D15SD
D14SD
D13SD
D12SD
D11SD
CN401
D10SD
N.U./FX8-60P-SV(71)
D+3.3VA
D9SD
GND
GND
D8SD
GND
GND
GND
GND
NC
NC
R613 10K/J2
NC
RDY/ BSY
PF6
WE
RESET
WR
R412 10K/J2
A19
A18
NC
A18
A17
A8
A9
D7SD
D6SD
A8
A7
A9
A10
D5SD
A6
A10
A7
A11
D4SD
A6
A5
A11
A12
D3SD
D2SD
A5
A4
A12
A13
D1SD
D0SD
A4
A3
A13
A14
A2
A14
A3
A15
A2
A1
A15
A16
A1
A0
A16
A17
CS00_FLASH
CE
BYTE
R413 10K/J2
GND
GND
RD
OE
D15
D7
D8
D0
D7
D15
D0
D8
D14
D6
D9
D1
D6
D14
D9
D13
D1
D5
D10
D2
D5
D13
D2
D10
D12
D4
D11
D3
D4
D12
7
D3
D11
VCC
TC7WH04FU
GND
GND
IC403:A
GND
GND
GND
GND
D.GND
D+3.3VA
CN402
FH12-16S-0.5SH
VCC
RESET OUT
RESET IN
TCK
TMS
TDI
TRST
TDO
WDTOVF
EMLE
EMLE
(SCK1)
SCK
RxD
RXD1
TxD
MD0
MD1
MD2
GND
TX
D.GND
R406
0/J2
REMOTE_TXD
D+3.3VA
R407
HD74LV2G126A
2200/J2
REMOTE_RXD
RX
HD74LV2G126A
D+3.3VA
R404
D.GND
0/J2
MD_SEL
VCC
GND
D.GND
D.GND
D+3.3VA
D+3.3VA
20
VCC
VCC
R436
100/J2
18
2
Y1
A1
RD
R437
100/J2
17
3
Y2
A2
WR
GND
R438
100/J2
16
4
Y3
A3
R439
100/J2
15
5
Y4
A4
A0
14
6
R440
100/J2
Y5
A5
A1
13
7
R441
100/J2
Y6
A6
A2
R442
100/J2
12
8
Y7
A7
A3
R443
100/J2
11
9
D.GND
Y8
A8
A4
C407
0.1U/Z2
1
OE1
R658
0/J2
10
19
GND
OE2
PF7
OE=Hi:Hi-Z
D.GND
D.GND
IC403:B
3V
TC7WH04FU
0V
3
5
D+3.3VA
IC441
TC7SH08FU
C482
IC415:C
0.1U/Z2
SN74AHC32PWR
CS1SD
CS11_SD
D.GND
A+3.3VA
245
IC408
DIR=H:AtoB
D+3.3VA
74LCX245MTCX
DIR=L:BtoA
20
VCC
G=H:Hi-Z
18
2
R426
100/J2
B1
A1
D15
R427
100/J2
17
3
B2
A2
D14
R428
100/J2
16
4
B3
A3
D13
R429
100/J2
15
5
B4
A4
D12
R430
100/J2
14
6
PG2
B5
A5
D11
13
7
R431
100/J2
PG3
B6
A6
D10
12
8
R432
100/J2
B7
A7
D9
R433
100/J2
11
9
B8
A8
D8
C405
0.1U/Z2
1
AN1
DIR
10
19
GND
G
AN3
AN5
D.GND
IC409
AN7
D+3.3VA
74LCX245MTCX
20
DA3
VCC
R418
100/J2
18
2
A.GND
B1
A1
D7
R419
100/J2
17
3
B2
A2
D6
R420
100/J2
16
4
B3
A3
D5
15
5
R421
100/J2
B4
A4
D4
14
6
R422
100/J2
B5
A5
D3
R423
100/J2
13
7
B6
A6
D2
R424
100/J2
12
8
B7
A7
D1
R425
100/J2
11
9
B8
A8
D0
C406
1
0.1U/Z2
DIR
10
19
GND
G
D.GND
D+3.3VA
D+3.3VA
EEPROM
VCC
SCL0
GND
SDA0
R444
C410
0/J2
0.1U/Z2
1
D.GND
D.GND
D.GND
D+3.3VA
IC405:B
TC74VHC08FT
4
6
CPU_RESET
5
PG4
D+3.3VA
PG5
IC405:A
PG6
TC74VHC08FT
1
3
P53
RESET
2
D+3.3VA
1
5
OUT
CD
2
SCL0
VDD
VCC
3
4
GND
NC
GND
TXD1
Reset IC
D.GND
D.GND
D+3.3VA
MD0
D+3.3VA
MD1
D+3.3VA
D.GND
D.GND
MD2
D.GND
D.GND
D+3.3VA
D+3.3VA
C414
0.1U/Z2
D+3.3VA
HD74LV2G126A
R456
R467
HD74LV2G126A
0/J2
N.U/J2
R457
X402
0/J2
CSTCE12M0G52-R0
D.GND
D+3.3VA
A l w a y s H i g h
R458
TC7S08FU
0/J2
SDCARD_CLK
HWR
LWR
D.GND
CPU_RESET
AN0
AN2
AN4
AN6
AN12
IC412
H8S2368F
PG4
PG5
PG6
TXD2
RXD2
SCK2
P53
SCL0
SDA0
RXD1
RXD0
TXD1
TXD0
MD0
MD1
D+3.3VA
IC415:A
SN74AHC32PWR
IC414
SN74AHC541PWR
R459
0/J2
100/J2
R481
MCD
R460
0/J2
100/J2
R482
SIDE_REMOTE
R461
0/J2
100/J2
R483
ROU_CHECK
R462
0/J2
100/J2
R484
INM_CHECK
R463
0/J2
100/J2
R485
CA_DET1
R464
0/J2
100/J2
R486
CA_DET2
R465
0/J2
100/J2
R487
VTR_DET1
R466
0/J2
100/J2
R488
VTR_DET2
・ S D C A R D D E T
・ S I D E R E M O T E
・ R O U C H E C K
D.GND
・ I N M C H E C K
・ C A D E T 1 , C A D E T 2 , V T R D E T 1 , V T R D E T 2
TP401
EYF6C(2125)
D+3.3VA
D401
DAN202K
R480
3
220/J2
B401
1
Time IC
+3V
BCR20H4(HOLDER)
2
CR2032(BATT)
IC411
S-35190A
1
8
INT
VDD
2
7
XOUT
SIO
3
6
XIN
SCK
4
5
VSS
CS
CS_RTC
SP-T2AF
X401
C416
C418
3P/C3
N.U/C3
D.GND
CY7C1011DV33
2Mbit SRAM
5
7
A1
A0
I/O0
4
8
A2
A1
I/O1
3
9
A3
A2
I/O2
2
10
A4
A3
I/O3
1
13
A4
I/O4
A5
44
14
A6
A5
I/O5
43
15
A7
A6
I/O6
42
16
A8
A7
I/O7
27
29
A9
A8
I/O8
26
30
A10
A9
I/O9
25
31
A10
I/O10
A11
24
32
A12
A11
I/O11
22
35
A13
A12
I/O12
21
36
A14
A13
I/O13
20
37
A15
A14
I/O14
19
38
A15
I/O15
A16
IC405:C
18
A17
A16
TC74VHC08FT
9
RD
8
40
28
BHE
NC
10
23
IC405:D
39
HWR
NC
D+3.3VA
BLE
TC74VHC08FT
12
17
WE
11
41
11
13
OE
VCC
LWR
6
33
CE
VCC
CS01_SRAM
12
WR
VSS
34
VSS
D.GND
IC421
RD
74LCX245MTCX
D+3.3VA
20
VCC
2
18
R516
100/J2
D0
A1
B1
DATA0
3
17
R517
100/J2
D1
A2
B2
DATA1
4
16
R518
100/J2
D2
A3
B3
DATA2
5
15
R519
100/J2
D3
A4
B4
DATA3
D+3.3VA
6
14
R520
100/J2
IC416
D4
A5
B5
DATA4
7
13
R521
100/J2
A6
B6
D5
DATA5
8
12
R522
100/J2
C429
D6
A7
B7
DATA6
9
11
R523
100/J2
D7
A8
B8
DATA7
0.1U/Z2
DIR=L : B to A(read)
C437
1
WR
DIR=H : A to B(write)
0.01U/Z2
RD
DIR
19
10
G
GND
CS03_FPGA
D.GND
D.GND
IC420
SN74AHC541PWR
D+3.3VA
20
VCC
2
18
R500
100/J2
A1
Y1
FPGA_CS
3
17
R501
100/J2
LWR
A2
Y2
VIDEO_WR
4
16
R502
100/J2
A3
Y3
VIDEO_RD
5
15
R503
100/J2
A1
A4
Y4
ADRS0
6
14
R504
100/J2
A2
A5
Y5
ADRS1
7
13
R505
100/J2
A6
Y6
A3
N.U/J2
ADRS2
R494
0/J2
8
12
R506
D+3.3VA
A7
Y7
R495
0/J2
9
11
R499
N.U/J2
A8
Y8
C433
1
0.1U/Z2
OE1
19
10
OE2
GND
D.GND
C425
3 b i t - 8 L i n e D e c o r d e r
IC417
0.1U/Z2
ChipSelect
o n e o f t h e m i s L o w
TC74VHC138FT
D+3.3VA
1
16
Low Active
A20
A
VCC
2
15
A21
B
Y0
CS00_FLASH
3
14
A22
C
Y1
CS01_SRAM
4
13
D7
R539
G2A
Y2
CS02_DSP
5
12
G2B
Y3
CS03_FPGA
D6
6
11
STBY
G1
Y4
D5
7
10
Y7
Y5
CS11_SD
8
9
D4
GND
Y6
CS12
D3
D2
D1
C434
D0
0.1U/Z2
SCK3
P27
P26
D.GND
IC423
P25
D.GND
SN74AHC574PW
RXD4
TXD4
20
VCC
P22
2
19
100/J2
D8
1D
1Q
3
18
P21
D9
2D
2Q
4
17
P20
D10
3D
3Q
5
16
P17
4D
4Q
D11
P16
6
15
100/J2
5D
5Q
D12
P15
7
14
100/J2
D13
6D
6Q
RXD1
IC415:B
8
13
100/J2
D14
7D
7Q
SN74AHC32PWR
9
12
TCLKB
D15
8D
8Q
TCLKA
HWR
11
P11
R493
CLK
P10
1
10
OC
GND
N.U/J2
IC403:C
WDTOVF
O P T I O N
TC7WH04FU
D.GND
6
2
( S H T _ E N )
STBY
R684
0/J2
C428
D+3.3VA
0.1U/Z2
D+5VA
D.GND
IC428:B
IC415:D
R543
NC7NZ04K8X
SN74AHC32PWR
0/J2
3
VCC
D.GND
GND
IC428:C
R542
NC7NZ04K8X
0/J2
6
D.GND
D.GND
D+3.3VA
RD
CS12
D.GND
D+3.3VA
IC418
TC74VHC138FT
D+3.3VA
D8
1
16
P20
A
VCC
2
15
100/J2
R524
D9
P21
B
Y0
R_STRB
3
14
D10
100/J2
R525
P22
C
Y1
4
13
D11
100/J2
R526
G2A
Y2
B_STRB
D12
5
12
N.U/J3
R527
G2B
Y3
D13
6
11
100/J2
R528
P25
G1
Y4
D14
7
10
100/J2
R529
Y7
Y5
8
9
100/J2
R530
D15
C427
GND
Y6
100/J2
R531
0.1U/Z2
C435
0.1U/Z2
D.GND
IC419
D+3.3VA
TC74VHC238FT
P20
100/J2
R508
P21
REAR_STRB
100/J2
R509
P22
100/J2
R510
SA_STRB1
100/J2
R511
100/J3
R512
P26
100/J2
R513
100/J2
R514
V_DA_STRB
100/J2
R515
R491
0/J3
PG2
C436
R492
0/J3
PG3
0.1U/Z2
0/J2
R532
D.GND
FRAME
0/J2
R533
SYS-HD
3V
0/J2
R534
HD,VD
0V
SYS-VD
D0
D+3.3VA
D1
D.GND
R498
D2
47K/D3
D3
REC_TALLY
D402
D4
DAN217
5V
D5
ON
OFF
3
D6
0V
D7
D8
2
D9
D10
D11
D12
D13
D.GND
D14
D15
R550
100/J2
P10
CCD_SCLK
R551
100/J2
P11
CCD_SDATA
R554
100/J2
P15
SA_SCLK
D+3.3VA
R555
100/J2
P16
SA_SDATA_IN
R556
100/J2
P17
SA_SDATA_OUT
D+3.3VA
R665
N.U./J2
BOX CAM
R675
R548
SW OK
0/J2
100/J2
TXD4
STATUS_TX
R666
N.U./J2
D+3.3VA
BOX CAM
N.U/J2
3V
SW OK
R549
0V
100/J2
RXD4
STATUS_RX
D.GND
D+3.3VA
D+3.3VA
R667
R655
TEMP_SNS_SEL
N.U./J2
BOX CAM
R668
R552
SW OK
R536
3V
0/J2
100/J2
CG_CS
R537
0V
SCK3
REAR_SCLK
R538
3V
CS_RTC
0V
R670
N.U./J2
D+3.3VA
R671
N.U./J2
BOX CAM
R672
R553
SW OK
0/J2
100/J2
R685
TXD3
REAR_SDATA
N.U./J2
R674
N.U./J2
D+5VA
D+3.3VA
5
BOX CAM
R557
SW OK
100/J2
RXD3
REAR_RX
2
D+3.3VA
D.GND
BOX CAM
SW OK
R653
R558
0/J2
100/J2
RXD2
IF_RX
R544
D.GND
100/J2
SCK2
SD_SCLK
R545
100/J2
TXD2
SD_SDATA
G_STRB
3V
0V
3V
LENS Digital Interface
[ASYNC]
IC428:A
MANUAL
0V
5V
R559
[ASYNC]
NC7NZ04K8X
0V
100/J2
1
7
TXD0
LENS_TX
R660
100/J2
FIL_STRB
R546
100/J2
PG0
FIL_SCLK
MIC_STRB
3V
SERVO
SA_STRB2
0V
5V
0V
TG_STRB
SERVO
R677
R547
0/J3
100/J2
IF_STRB
PG1
FIL_SDATA
MANUAL
3V
PF2
0V
D.GND
R679
R680
TCLKA
N.U/J3
N.U/J3
TCLKB
R512
R527
R547
R680
R677
R679
SERVO
Used
N.U.
D.GND
MANUAL
N.U.
Used
PF1
R683
R682
0/J2
100/J2
PF0
FPGA_ROM_Q
1
SK-HD1300-S3
CPU-HD1K (PT-X2330D) (1/2)
SCHEMATIC DIAGRAM
6-57
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