Gpio Registers; Table 5-9 Gpio Registers - GE C2K Hardware Reference Manual

5.2.3 GPIO Registers

The C2K includes 16 General-Purpose Input/Output ports. The FPGA provides the GPIO inter-
rupt masking, data, and control registers for configuring, masking interrupts, and sending/receiv-
ing data on the GPIO lines connected to the backplane. The FPGA also includes an optional
de-bounce circuit that can be applied to each port designated as an input for use with external
switches, contacts, or relays. The GPIO registers set the following configuration parameters:
• Direction (input or output)
• Output drive type (TTL or open-drain)
• Input polarity (inverted or non-inverted)
• Interrupt type (edge or level-sensitive)
• Debounce filter on input
When the GPIO lines are configured as outputs, they can be driven as either standard TTL or
open-drain (drive-low only). When configured as inputs, the GPIO lines can be treated as positive
or negative logic and can be enabled as either edge or level-type interrupt sources for generating
the MPC7448 processor's interrupt input (the FPGA interrupt output passes through the
MV64460 interrupt logic). The selected logic polarity for GPIO inputs affects the value read in
the GPIO Data Register and affects which logic level will cause an interrupt assertion. The regis-
ters' default bit values occur after a power-up reset.
Table 5-9 lists the GPIO registers.
GPIO registers
Table 5-9
Offset Register
0x30 GPIO Direction
0x32 GPIO Polarity
0x34 GPIO Output Type
0x36 GPIO Interrupt Type
0x38 GPIO De-Bounce Enable Enables a de-bounce circuit for each GPIO line.
0x40 GPIO Input Data Read
0x42 GPIO IO Data
0x44 GPIO Interrupt Status
0x46 GPIO Interrupt Mask
0x4C GPIO Clear
0x4E GPIO Set
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Description
Enables a direction for each GPIO line.
Enables polarity for each GPIO line.
Enables output type for each GPIO line.
Configures each interrupt for type (edge, level)
Enables input data read for each GPIO line.
Enable input IO data state for each GPIO line.
Provides the interrupt status for each GPIO line.
Enables interrupt masking for each GPIO line.
Clears the GPIO bit for each GPIO line.
Sets the GPIO bit for each GPIO line.
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