GE C2K Hardware Reference Manual page 108

Bits Field
7 CNTR7_INT_MSK
6 CNTR6_INT_MSK
5 CNTR5_INT_MSK
4 CNTR4_INT_MSK
3 CNTR3_INT_MSK
2 CNTR2_INT_MSK
1 CNTR1_INT_MSK
0 CNTR0_INT_MSK
Counter Interrupt Status Register
The Counter Interrupt Status Register provides interrupt status information for each counter.
Address offset: 0x58
Access: Read/clear
Bits Field
15 CNTR15_INT_STAT
14 CNTR14_INT_STAT
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Default
1 Counter 7 Interrupt Mask—blocks (masks) the interrupt for
counter 7.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 6 Interrupt Mask—blocks (masks) the interrupt for
counter 6.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 5 Interrupt Mask—blocks (masks) the interrupt for
counter 5.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 4 Interrupt Mask—blocks (masks) the interrupt for
counter 4.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 3 Interrupt Mask—blocks (masks) the interrupt for
counter 3.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 2 Interrupt Mask—blocks (masks) the interrupt for
counter 2.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 1 Interrupt Mask—blocks (masks) the interrupt for
counter 1.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 0 Interrupt Mask—blocks (masks) the interrupt for
counter 0.
0 = enable interrupt
1 = disable (mask) interrupt
Default
- Counter 15 Interrupt Status—provides current interrupt status
for counter 15.
0 = interrupt is de-asserted
1 = interrupt is asserted
- Counter 14 Interrupt Status—provides current interrupt status
for counter 14.
0 = interrupt is de-asserted
1 = interrupt is asserted
Description
Description
Resources
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