Usart Divisor Latch Registers; Table 5-13 Baud-Rate Divisor Settings - GE C2K Hardware Reference Manual

5.2.7 USART Divisor Latch Registers

The USART includes a programmable baud-rate generator to divide the reference clock down to
the serial data rate. The divisor is a 16-bit value contained in two byte-wide registers: one for the
MSB and one for the LSB. In asynchronous mode, the clock is set to 16 x the bit rate, while in the
synchronous mode, the clock is set to 1 x the bit rate.
USART Divisor (LSB) Register
Address offset: USART + Base +0x0
DLAB: 1
Access: Read/write
Bit(s) Field
7 - 0 DIV[7–0]
USART Divisor (MSB) Register
Address offset: USART + Base + 0x2
DLAB: 1
Access: Read/write
Bit(s) Field
7 - 0 DIV[15–8]
Table 5-13 shows the divisor values for some common serial data rates with a 14.7692MHz
(48.0MHz x 4 /13) reference clock.
Baud-rate divisor settings
Table 5-13
Baud Sync
Rate Mode
300 0
1200 0
2400 0
9600 0
19200 0
38400 0
57600 0
115.2k 0
230.4k 0
460.8k 0
921.6k 1
1.8432M 1
3.6864M 1
5-53
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Default
0x00 LSB of baud-rate generator divisor.
Default
0x00 MSB of baud-rate generator divisor.
Frequency
Divisor
Error (%)
3076 +0.03
770 +0.16
384 +0.16
96 +0.16
48 +0.16
24 +0.16
16 +0.16
8 +0.16
4 +0.16
2 +0.16
16 +0.16
8 +0.16
4 +0.16
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