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Table 3-4 PC/104 ISA Bus Pin Assignment
3.2.7 CPU Setting
The AR-B1474 accepts many types of microprocessor, such as INTEL/AMD/CYRIX 486DX/DX2/DX4. All of these
CPUs include an integer processing unit, floating-point processing unit, memory-management unit, and cache.
They can give a two to ten-fold performance improvement in speed over the 386 processor, depending on the
clock speeds used and specific application. Like the 386 processor, the 486 processor includes both segment-
based and page-based memory protection schemes. Instruction processing time is reduced by on-chip instruction
pipelining. By performing fast, on-chip memory management and caching, the 486 processor relaxes requirements
for memory response for a given level of system performance.
(1) AMD DX2-80 CPU Select (JP1)
(2) CPU Voltage Select (JP2)
(3) AMD 4X CPU (5x86) Select (JP15)
Name
-MASTER [Input]
The MASTER is the signal from the I/O processor which
gains control as the master and should be held low for a
maximum of 15 microseconds or system memory may be
lost due to the lack of refresh
-MEMCS16
The Memory Chip Select 16 indicates that the present
[Input, Open collector]
data transfer is a 1-wait state, 16-bit data memory
operation
-IOCS16
The I/O Chip Select 16 indicates that the present data
[Input, Open collector]
transfer is a 1-wait state, 16-bit data I/O operation
OSC [Output]
The Oscillator is a 14.31818 MHz signal
-ZWS
The Zero Wait State indicates to the microprocessor that
[Input, Open collector]
the present bus cycle can be completed without inserting
additional wait cycle
JP1
1 2 3
AMD DX2-80
Figure 3-11 JP1: AMD DX2-80 CPU Select
1 2 3
1 3 5
3.3V
Figure 3-12 JP2: CPU Voltage Select
1 2 3
AMD CPU
Figure 3-13 JP15: AMD 4X CPU (5x86) Select
Description
1 2 3
Others CPU
JP2
1 2 3
1 3 5
5V
JP15
1 2 3
Others CPU
AR-B1474 User¡ ¦ s Guide
3-7
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