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Artesyn ATCA-7475 Installation And Use Manual

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ATCA-7475
Installation and Use
P/N: 6806800S38D
May 2014

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  • Page 1 ATCA-7475 Installation and Use P/N: 6806800S38D May 2014...
  • Page 2 Artesyn reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes.

  • Page 3: Table Of Contents

    3.1.3 Connectors..............67 ATCA-7475 Installation and Use (6806800S38D)
  • Page 4 IPMI Support ..............101 ATCA-7475 Installation and Use (6806800S38D)
  • Page 5 5.12 Serial Over LAN ..............131 ATCA-7475 Installation and Use (6806800S38D)
  • Page 6 6.4.10.2 Reset Mask Register ..........156 ATCA-7475 Installation and Use (6806800S38D)
  • Page 7 6.4.26.3 Telecom Clock Monitor Registers ........186 ATCA-7475 Installation and Use (6806800S38D)
  • Page 8 9.2.1 Set/Get Power Level ............222 Artesyn Embedded Technologies Specific Commands ....... . . 223 9.3.1 Serial Output Commands .
  • Page 9 10.4 Sensor Data Records ............. . . 254 ATCA-7475 Installation and Use (6806800S38D)
  • Page 10 Related Documentation ............. . 279 Artesyn Embedded Technologies - Embedded Computing Documentation ....279 Manufacturers’...
  • Page 11 Memory Information Definition ..........108 ATCA-7475 Installation and Use (6806800S38D)
  • Page 12 RTM SPI Read Register ............154 ATCA-7475 Installation and Use (6806800S38D)
  • Page 13 Misc (Ethernet Link and CPU Error) Status Register ....... . 182 ATCA-7475 Installation and Use (6806800S38D)
  • Page 14 System Boot Options - Parameter #100 - Data Format ......213 ATCA-7475 Installation and Use (6806800S38D)
  • Page 15 Get Module State Command Description ........246 ATCA-7475 Installation and Use (6806800S38D)
  • Page 16 Artesyn ECC MAC Address Record ........
  • Page 17 Interrupt Structure on ATCA-7475 ........
  • Page 18 Location of On-board Battery ..........276 ATCA-7475 Installation and Use (6806800S38D)

  • Page 19: About This Manual

    FRU Information and Sensor Data Records on page 251, provides information on the blade’s  FRU information and sensor data. Firmware Upgrade on page 269, provides information on how to upgrade the firmware  components. ATCA-7475 Installation and Use (6806800S38D)
  • Page 20 Electrostatic Sensitive Device FPGA Field-Programmable Gate Array Ground IPMB Intelligent Platform Management Bus IPMC Intelligent Platform Management Controller IPMI Intelligent Platform Management Interface Industry Standard Architecture Light Emitting Diode Media Access Control NEBS Network Equipment Building System ATCA-7475 Installation and Use (6806800S38D)
  • Page 21 Restriction of the use of Certain Hazardous Substances Serial Attached SCSI SATA Serial ATA SCSI Small Computer System Interface Sensor Data Record Serial Management Interface Serial-over-LAN Serial Presence Detect Serial Peripheral Interface SRAM Static Random Access Memory Universal Serial Bus ATCA-7475 Installation and Use (6806800S38D)
  • Page 22 Repeated item for example node 1, node 2, ..., node Omission of information from example/command that is not necessary at the time being Ranges, for example: 0..4 means one of the integers 0,1,2,3, and 4 (used in registers) Logical OR ATCA-7475 Installation and Use (6806800S38D)

  • Page 23: Table

    EMV on page 6806800S38C January 2014 Updated Table "Blade Variants" on page Table "Critical Temperature Limits" on page 47 Table "Power Requirements" on page Updated Processor on page 122. 6806800S38D May 2014 Re-branded to Artesyn template. ATCA-7475 Installation and Use (6806800S38D)
  • Page 24 About this Manual About this Manual ATCA-7475 Installation and Use (6806800S38D)

  • Page 25: Safety Notes

    The blade has been tested in a standard Artesyn Embedded Technologies system and found to comply with the limits for a Class A digital device in this system, pursuant to part 15 of the FCC Rules, EN 55022 Class A respectively.
  • Page 26 Damage of Blade and Additional Devices and Modules Incorrect installation of additional devices or modules may damage the blade or the additional devices or modules. Before installing or removing an additional device or module, read the respective documentation ATCA-7475 Installation and Use (6806800S38D)
  • Page 27 When operating the blade, make sure that forced air cooling is available in the shelf. When operating the blade in areas of electromagnetic radiation ensure that the blade is bolted on the system and the system is shielded by enclosure. Injuries or Short Circuits Blade or power supply ATCA-7475 Installation and Use (6806800S38D)
  • Page 28 Therefore, always use the same type of Lithium battery as is installed and make sure the battery is installed as described in this manual. Environment Always dispose of used blades, system components and RTMs according to your country’s legislation and manufacturer’s instructions. ATCA-7475 Installation and Use (6806800S38D)

  • Page 29: Sicherheitshinweise

    Installieren Sie keine Ersatzteile oder führen Sie keine unerlaubten Veränderungen am Produkt durch, sonst verfällt die Garantie. Wenden Sie sich für Wartung oder Reparatur bitte an die für Sie zuständige Geschäftsstelle von Artesyn Embedded Technologies. So stellen Sie sicher, dass alle sicherheitsrelevanten Aspekte beachtet werden.
  • Page 30 Sicherheitshinweise Das Blade wurde in einem Artesyn Embedded Technologies Standardsystem getestet. Es erfüllt die für digitale Geräte der Klasse A gültigen Grenzwerte in einem solchen System gemäß den FCC-Richtlinien Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen angemessenen Schutz vor Störstrahlung beim Betrieb des Blades in Gewerbe- sowie...
  • Page 31 Hohe Luftfeuchtigkeit und Kondensat auf der Oberfläche des Blades können zu Kurzschlüssen führen. Betreiben Sie das Blade nur innerhalb der angegebenen Grenzwerte für die relative Luftfeuchtigkeit und Temperatur. Stellen Sie vor dem Einschalten des Stroms sicher, dass sich auf dem Blade kein Kondensat befindet. ATCA-7475 Installation and Use (6806800S38D)
  • Page 32 ändern Sie die Einstellungen der nicht mit 'Reserved' gekennzeichneten Schalter, bevor Sie das Blade installieren. Beschädigung der Blade Das Verstellen von Schaltern während des laufenden Betriebes kann zur Beschädigung des Blades führen. Prüfen und ändern Sie die Schaltereinstellungen, bevor Sie das Blade installieren. ATCA-7475 Installation and Use (6806800S38D)
  • Page 33 Verwenden Sie deshalb nur den Batterietyp, der auch bereits eingesetzt wurde und befolgen Sie die Installationsanleitung. Umweltschutz Entsorgen Sie alte Batterien und/oder Blades/Systemkomponenten/RTMs stets gemäß der in Ihrem Land gültigen Gesetzgebung und den Empfehlungen des Herstellers. ATCA-7475 Installation and Use (6806800S38D)
  • Page 34 Sicherheitshinweise ATCA-7475 Installation and Use (6806800S38D)

  • Page 35: Introduction

    Chapter 1 Introduction Features The ATCA-7475 is a high-performance ATCA compliant single board computer designed for demanding storage and processing applications. The main features of the ATCA-7475 board are as follows: Designed for NEBS level 3  Dual socket Intel Xeon E5-2600 V2 ...

  • Page 36: Standard Compliances

    Description UL 60950-1 Legal safety requirements EN 60950-1 IEC 60950-1 CAN/CSA C22.2 No 60950-1 CISPR 22 EMC requirements on system level (predefined Artesyn Embedded Technologies system) CISPR 24 EN 55022 EN 55024 FCC Part 15 EN 300386 NEBS Standard GR-1089 CORE...

  • Page 37: Figure 1-1 Declaration Of Conformity

    Introduction The following figure is the copy of Declaration of Conformity for ATCA-7475. Figure 1-1 Declaration of Conformity ATCA-7475 Installation and Use (6806800S38D)

  • Page 38: Mechanical Data

    The following table provides details about the mechanical data of the blade, such as dimensions and weight. Table 1-2 Mechanical Data Feature Value Dimensions (width x height x depth) 30 mm x 351 mm x 312 mm 8U form factor Weight of blade 3.2 kg ATCA-7475 Installation and Use (6806800S38D)

  • Page 39: Product Identification

    The following figure shows the location of the serial number label. Figure 1-2 Serial Number Location Ordering Information The ATCA-7475 is a high performance ATCA compliant single board computer designed for demanding storage and processing applications. ATCA-7475 Installation and Use (6806800S38D)

  • Page 40: Table 1-3 Blade Variants

    Introduction The following table lists the blade variants that are available upon release of this publication. Consult your local Artesyn Embedded Technologies sales representative for the availability of other variants. Table 1-3 Blade Variants Product Name Description ATCA-7475-0GB ATCA-7475 Blade with Dual Intel Xeon E5-2648L V2 10-Core @1.9GHz processors (Ivy Bridge 70W TDP), 2.5MB per Core Last Level Cache,...
  • Page 41 Introduction Table 1-4 Blade Accessories (continued) Accessory Description ATCA-7XMMOD-SATA2 64 GB SLC SLIM SATA (MO-297) on-board solid state disk module SA-BBS-WR43-7475 DVD - BBS SW and WindRiver Linux 4.3 for ATCA-7475 ATCA-7475 Installation and Use (6806800S38D)
  • Page 42 Introduction ATCA-7475 Installation and Use (6806800S38D)

  • Page 43: Hardware Preparation And Installation

    Environmental and Power Requirements In order to meet the environmental requirements, the blade has to be tested in the system in which it is to be installed. ATCA-7475 Installation and Use (6806800S38D)

  • Page 44: Environmental Requirements

    Blade Overheating and Blade Damage Operating the blade without forced air cooling may lead to blade overheating and thus blade damage. When operating the blade, make sure that forced air cooling is available in the shelf. ATCA-7475 Installation and Use (6806800S38D)

  • Page 45: Table 2-1 Environmental Requirements

    Random 20-200Hz at 3 m Shock Half-sine, 11 ms, 30 m/s Blade level packaging Half-sine, 6 ms at 180 m/s Free Fall 1.2 m/ packaged (according to ETSI 300 019-2-2) 100 mm unpackaged (according to Telcordia GR-63-core) ATCA-7475 Installation and Use (6806800S38D)

  • Page 46: Figure 2-1 Location Of Critical Temperature Spots (Blade Top Side)

    Temperature Spot 2 (on 48 DC/DC Converter) Temperature Spot 1 (on Power Entry Module) Max: 100°C , (exact location: in the geometric Max: 110°C , (exact location: on top of upper middle of the heat spreader) transformer housing) ATCA-7475 Installation and Use (6806800S38D)

  • Page 47: Power Requirements

    In the following table you will find typical examples of power requirements with and without accessories installed. For information on the accessories' power requirements, refer to the documentation delivered together with the respective accessory or consult your local Artesyn Embedded Technologies representative for further details. ATCA-7475 Installation and Use (6806800S38D)

  • Page 48: Table 2-3 Power Requirements

    Operating Voltage -39 VDC to -72 VDC Exception in the US and Canada -39 VDC to -60 VDC Max. power consumption of ATCA-7475 (with ATCA- All product variants except ATCA-7475- 7470-ACCEL-MOD and with RTM-ATCA-736x-10G xGB-CE: 250W (typ. 215W) including SAS HDD) ATCA-7475-xGB-CE variant: 300W (typ.
  • Page 49 There is also a dependency on the batch variance of the major components like the processor and DIMMs used. Hence, Artesyn does not represent or warrant that measurement results of a specific board provide guaranteed maximum values for a series of boards.

  • Page 50: Blade Layout

    Hardware Preparation and Installation Blade Layout The following figure shows the location of components on the ATCA-7475: Figure 2-2 ATCA-7475 Blade Layout ATCA-7475 Installation and Use (6806800S38D)

  • Page 51: Switch Settings

    Switches reside on the component side 1 and are not covered by any other component. Their location is shown in the following figure: Figure 2-3 Switch Location (Bottom Side of the Blade) ATCA-7475 Installation and Use (6806800S38D)

  • Page 52: Table 2-4 Switch Sw1 Settings

    3-pin Header SW2.3 FPGA_PROM_SEL OFF (1) Use standard download PROM or redundant OFF = High => Use default FPGA EEPROM download PROM for FPGA ON = Low => Use Fail-Safe FPGA EEPROM configuration SW2.4 Reserved ATCA-7475 Installation and Use (6806800S38D)

  • Page 53: Table 2-6 Switch Sw3 Settings

    ON disable reboot feature SW4.3 [SW4.4, SW4.3] The Default is 00 - Normal operation 00 - Normal operation SW4.4 01 - Reserved 10 - Load BIOS Defaults 11 - Port80 to COM1 ATCA-7475 Installation and Use (6806800S38D)

  • Page 54: Installing The Blade Accessories

    Ranked RDIMM) are allowed. The reason is the thermal limit/budget of the blade and the high variation of the power consumptions of different DIMM types. For thermal reasons, no 4-rank DIMMs and no dual-Die DIMM are allowed. ATCA-7475 supports low-voltage DDR3 memory. This is available upon request. ATCA-7475 Installation and Use (6806800S38D)
  • Page 55 Hardware Preparation and Installation ATCA-7475 has 1 DIMM socket per Xeon memory channel. Therefore usage of 2-rank DIMMs are essential for best performance. Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life.

  • Page 56: Mo297 Ssd Module

    The SATA module consists of a Solid State Disc of up to 256 GB and a SATA controller and connects physically to PCH Sata Port #4. The MO297 SSD module is an accessory kit and is not part of the default ATCA-7475. The following procedure describes the steps to install/remove the MO297 SSD module.
  • Page 57 2. Remove the two screws holding the MO297 SSD module 3. Remove the from the blade. MO297 SSD module 4. Reinstall the blade into the system as described in Installing and Removing the Blade on page ATCA-7475 Installation and Use (6806800S38D)

  • Page 58: Accelerator Module

    Hardware Preparation and Installation 2.5.3 Accelerator Module The ATCA-7475 provides the possibility to assemble the ATCA-7470-Accelerator module. The ATCA-7470-Accelerator module is equipped with two additional Intel DH8920CC SKU4 PCH devices. Installation Procedure Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life.

  • Page 59: Installing And Removing The Blade

    Incorrect blade installation and removal can result in blade malfunctioning. When plugging the blade in or removing it, do not press on the face plate but use the handles. 2.6.1 Installing the Blade To install the blade into an AdvancedTCA shelf, proceed as follows. ATCA-7475 Installation and Use (6806800S38D)
  • Page 60 Continue to gently push the blade until the blade connectors engage. 4. Squeeze the lever and the latch together and hook the lower and the upper handle into the shelf rail recesses. ATCA-7475 Installation and Use (6806800S38D)
  • Page 61 The switched off blue LED indicates that the blade’s payload has been powered up and that the blade is active. 7. Connect cables to the face plate, if applicable. ATCA-7475 Installation and Use (6806800S38D)

  • Page 62: Removing The Blade

    2. Wait until the blue LED is illuminated permanently, then unlatch the upper handle and rotate both handles fully outward. If the LED continues to blink, a possible reason may be that the upper layer software has rejected the blade extraction request. ATCA-7475 Installation and Use (6806800S38D)
  • Page 63 Wait until the blue LED is permanently illuminated, before removing the blade. 3. Remove the face plate cables, if applicable. 4. Unfasten the screws of the face plate until the blade is detached from the shelf. 5. Remove the blade from the shelf. ATCA-7475 Installation and Use (6806800S38D)
  • Page 64 Hardware Preparation and Installation ATCA-7475 Installation and Use (6806800S38D)

  • Page 65: Controls, Indicators, And Connectors

    Chapter 3 Controls, Indicators, and Connectors Face Plate The following figure illustrates the connectors, keys, and LEDs available at the face plate: Figure 3-1 Face Plate ATCA-7475 ATCA-7475 Installation and Use (6806800S38D)

  • Page 66: Leds

    Green: Link is available Off: No link Activity (lower) Yellow: Activity Off: No activity U1, U2 Base interface activity is visualized via FPGA LEDs U1 and U2 User LED, selectable color via FPGA register. Colors: red, green, amber ATCA-7475 Installation and Use (6806800S38D)

  • Page 67: Keys

    On pressing it, a hard reset is triggered and all attached on-board devices are reset. You cannot reset the IPMC via this key. 3.1.3 Connectors The blade provides the following connectors at its face plate: 2x Ethernet  1x Serial  2x USB  ATCA-7475 Installation and Use (6806800S38D)

  • Page 68: Serial Com#1 P17

    3.1.3.1 Serial COM#1 P17 Serial line interface #1 of Glue Logic FPGA is available at the faceplate of ATCA-7475. A female RJ45 connector is used for serial line connection. Cisco-like Pinout according following table is used.Additinally Hardware Handshake support signals are available.

  • Page 69: Serial Interface Connector

    SW2-1 also changes the serial connector that you need to access to make use of the serial redirection feature. The pinout of the serial interface connector is shown below. Figure 3-3 Serial Interface Connector Pinout ATCA-7475 Installation and Use (6806800S38D)

  • Page 70: Usb Connectors

    Figure 3-4 USB Connector Pinout Attaching a device to the front panel USB ports that exceeds the maximum USB current rating of 500mA per port will result in the ATCA-7475 protecting itself through a controlled board shutdown. On-board Connectors The blade provides the following on-board connectors: MO297 SSD module connector ...

  • Page 71: Figure 3-5 Location Of Mo297 Ssd Module Connector

    Controls, Indicators, and Connectors The location of the MO297 SSD module connector is illustrated in the following figure. Figure 3-5 Location of MO297 SSD Module Connector ATCA-7475 Installation and Use (6806800S38D)

  • Page 72: Figure 3-6 Mo297 Ssd Module Connector Pinout

    Controls, Indicators, and Connectors The pinout of this connector is illustrated in the following figure. Figure 3-6 MO297 SSD Module Connector Pinout SATA_TX+ SATA_TX- SATA_RX+ SATA_RX- S1,S4,S7 P4,P5,P6,P10,P12 +3.3V P1,P2,P3 P7,P8,P9 +12V P13,P14,P15 ATCA-7475 Installation and Use (6806800S38D)

  • Page 73: Advancedtca Backplane Connectors

    Location of AdvancedTCA Connectors The connector residing in zone 1 is called P10 and carries the following signals: Power feed for the blade (VM48_x_CON and RTN_x_CON)  Power enable (ENABLE_x)  IPMB bus signals (IPMB0_x_yyy)  ATCA-7475 Installation and Use (6806800S38D)

  • Page 74: Figure 3-8 P10 Backplane Connector Pinout

    P10 Backplane Connector Pinout Zone 2 contains the two connectors P20 and P23. They carry the following types of signals: Telecom clock signals (CLKx_)  Base interface signals (BASE_)  SAS update channel  100Base-BX update channel  ATCA-7475 Installation and Use (6806800S38D)

  • Page 75: Figure 3-9 P20 Backplane Connector Pinout - Rows A To D

    In all other cases the pins are unconnected and consequently marked as "n.c.". The pinouts of P20 and P23 are as follows. Figure 3-9 P20 Backplane Connector Pinout - Rows A to D Figure 3-10 P20 Backplane Connector Pinout - Rows E to H ATCA-7475 Installation and Use (6806800S38D)

  • Page 76: Figure 3-11 P23 Backplane Connector Pinout - Rows A To D

    Zone 3 contains the two connectors P30, P31, and P32. They are used to connect an RTM to the blade and carry the following signals: Serial (RS232_x_yyyy)  Serial ATA (SATAx_yyy)  USB (USBxy)  ATCA-7475 Installation and Use (6806800S38D)

  • Page 77: Figure 3-13 P30 Backplane Connector Pinout - Rows A To D

    SAS Update channels  General control signals (BD_PRESENTx, RTM_PRSNT_N, RTM_RST_KEY-, RTM_RST-)  Figure 3-13 P30 Backplane Connector Pinout - Rows A to D Figure 3-14 P30 Backplane Connector Pinout - Rows E to H - ATCA-7475 Installation and Use (6806800S38D)

  • Page 78: Figure 3-15 P31 Backplane Connector Pinout - Rows A To D

    P31 Backplane Connector Pinout - Rows E to H PCIE_CPU1_P3_RX_N<1> PCIE_CPU1_P3_RX_P<1> PCIE_CPU1_P3_TX_P<1> PCIE_CPU1_P3_TX_N<1> PCIE_CPU1_P3_RX_N<3> PCIE_CPU1_P3_RX_P<3> PCIE_CPU1_P3_TX_P<3> PCIE_CPU1_P3_TX_N<3> PCIE_CPU1_P3_RX_N<5> PCIE_CPU1_P3_RX_P<5> PCIE_CPU1_P3_TX_P<5> PCIE_CPU1_P3_TX_N<5> PCIE_CPU1_P3_RX_N<7> PCIE_CPU1_P3_RX_P<7> PCIE_CPU1_P3_TX_P<7> PCIE_CPU1_P3_TX_N<7> PCIE_CPU1_P3_RX_N<9> PCIE_CPU1_P3_RX_P<9> PCIE_CPU1_P3_TX_P<9> PCIE_CPU1_P3_TX_N<9> PCIE_CPU1_P3_RX_N<11> PCIE_CPU1_P3_RX_P<11> PCIE_CPU1_P3_TX_P<11> PCIE_CPU1_P3_TX_N<11> PCIE_CPU1_P3_RX_N<13> PCIE_CPU1_P3_RX_P<13> PCIE_CPU1_P3_TX_P<13> PCIE_CPU1_P3_TX_N<13> PCIE_CPU1_P3_RX_N<15> PCIE_CPU1_P3_RX_P<15> PCIE_CPU1_P3_TX_P<15> PCIE_CPU1_P3_TX_N<15> n.c. ATCA-7475 Installation and Use (6806800S38D)

  • Page 79: Figure 3-17 P32 Backplane Connector Pinout - Rows A To D

    Controls, Indicators, and Connectors Figure 3-17 P32 Backplane Connector Pinout - Rows A to D - Figure 3-18 P32 Backplane Connector Pinout - Rows E to H - ATCA-7475 Installation and Use (6806800S38D)
  • Page 80 Controls, Indicators, and Connectors ATCA-7475 Installation and Use (6806800S38D)

  • Page 81: Bios

    System Boot Options Parameter #96 on page 210. The BIOS used on the blade is based on the Phoenix UEFI BIOS with several Artesyn Embedded Technologies extensions integrated. Its main features are: Initialize CPU, chipset and memory ...

  • Page 82: Accessing The Blade Using The Serial Console Redirection

    Terminal emulation programs such as TeraTermPro or Putty can be used. 4.2.2 Default Access Parameters By default, the blade can be accessed using the serial interface COM1. By default, this interface is accessible using a RJ-45 connector at the blade's face plate. ATCA-7475 Installation and Use (6806800S38D)

  • Page 83: Connecting To The Blade

    3. Connect NULL-modem cable to COM port of the blade. 4. Start up the blade. Changing Configuration Settings When the system is switched on or rebooted, the presence and functionality of the system components is tested by Power-On Self-Test (POST). ATCA-7475 Installation and Use (6806800S38D)

  • Page 84: Main Menu

    In order to navigate in setup, use the arrow keys on the keyboard to highlight items on the menu. All other navigation possibilities are shown at the bottom of the menu. Additionally, an item-specific help is displayed on the right side of the window. ATCA-7475 Installation and Use (6806800S38D)

  • Page 85: Boot Options

    There are two possibilities to determine the device from which BIOS attempts to boot: By setup, to select a permanent order of boot devices  By boot selection menu, to select any device for the next boot-up procedure only  ATCA-7475 Installation and Use (6806800S38D)
  • Page 86 If BIOS is not successful at booting from one device, it tries to boot from the next device on the list. When BIOS does not find any bootable device, the board will be restarted by a cold reset. ATCA-7475 Installation and Use (6806800S38D)

  • Page 87: By Boot Menu

    1. Press F4 to enter the Boot Menu. Figure 4-2 Boot Menu 2. Override existing boot sequence by selecting another boot device from the boot list. If the selected device does not load the operating system, BIOS returns to the boot menu. ATCA-7475 Installation and Use (6806800S38D)

  • Page 88: Ipmi Boot Parameter

    Normally, the BIOS setup parameters are stored within the BIOS flash. The following figure and description helps you to understand how a BIOS setup parameter and an IPMI boot parameter interact. Figure 4-3 IPMI Boot Parameter ATCA-7475 Installation and Use (6806800S38D)

  • Page 89: Restoring Bios Default Settings

    The blade provides an on-board configuration switch that allows to load BIOS settings from the DEFAULT area of the IPMI Boot Parameters. In order to restore the BIOS default settings using this switch, you have to proceed as follows: ATCA-7475 Installation and Use (6806800S38D)

  • Page 90: Bios Setup Configuration

    RTM Network Ethernet controller. Select Enabled when RTM Network Boot is required. ARTM SAS Boot Enabled (Default), Controls execution of the Option ROM for Disabled RTM SAS controller. Select Enabled when RTM SAS Boot is required. ATCA-7475 Installation and Use (6806800S38D)

  • Page 91: Advanced

    Zone 3 connector (RTM). CPU0 PCIe to RTM Speed Auto (Default), Selects CPU0 PCIe Speed for Zone 3 Gen1,Gen2,Gen3 connector (RTM).Auto: uses the highest possible PCIe speed Gen1: 2.5 GT/s Gen2: 5 GT/s Gen3: 8 GT/s ATCA-7475 Installation and Use (6806800S38D)

  • Page 92: Table 4-4 Advanced --> Cpu Configuration

    Enable/Disable processor Turbo Mode. Disable Turbo Mode is only available when Speed Step is enabled. C-States Enable (Default) Enable/Disable processor idle power saving Disable states (C-States) C3-State Enable Enable/Disable processor idle power saving Disable (Default) C3 state ATCA-7475 Installation and Use (6806800S38D)

  • Page 93: Table 4-6 Advanced --> Cpu Configuration -> System Agent (Sa) Configuration

    Enable Pair's physical channels (primary and Disable (Default) secondary) to form one logical channel. The secondary channel contains a copy of the in the primary channel. Channel Mirroring and Channel Lockstep mode is mutually exclusive. ATCA-7475 Installation and Use (6806800S38D)
  • Page 94 ECC errors constitute a flood condition PCIe AER Errors Log Enable Controls whether PCIe Advanced Error Disable (Default) Reporting (AER) errors are logged PCIe Error Flood Enable Enable/Disable PCIe Error Flood Count Disable (Default) ATCA-7475 Installation and Use (6806800S38D)

  • Page 95: Table 4-9 Advanced --> Usb Configuration

    Table 4-11 Advanced --> Super IO Configuration Item Values Description UART1 to Front Panel Enable (Default) This option controls the UART1. When Disable enabled, ART1 uses address 3F8h and IRQ 4. UART1 is connected to the front panel. ATCA-7475 Installation and Use (6806800S38D)

  • Page 96: Ipmi

    OS. The OS has to shut off the watchdog timer when successfully booted. O/S Watchdog Timer 1, 2, 3, 4, 7, 10, 15, 20 Configure the Timeout of the O/S Boot Timeout minutes Watchdog Timer. Default: 5 minutes ATCA-7475 Installation and Use (6806800S38D)

  • Page 97: Security

    Enact TPM Action. Note: Most TPM actions require TPM to be Enabled to take effect. Omit Boot Measurement Enabled Enabling this option causes the system to Disabled (Default) omit recording boot device attempts in PCR[4]. ATCA-7475 Installation and Use (6806800S38D)

  • Page 98: Boot

    In order to get optimal performance for packet switching applications, it is recommended to set following CPU configuration parameter (seeAppendix 4, Advanced --> CPU Configuration): Table 4-16 CPU Performance Settings Parameters Settings Direct Cache Access Enabled ATCA-7475 Installation and Use (6806800S38D)

  • Page 99: Memory Configuration

    For other applications it might be better to set different values, especially when power savings are desired. 4.7.8 Memory Configuration The ATCA-7475 supports three different memory RAS (Reliability, Availability, and Serviceability) modes: Independent Channel Mode, Mirrored Channel Mode, and Lockstep Channel Mode. 4.7.8.1 Independent Channel Mode In independent mode, all four channels are operating independently.

  • Page 100: Lockstep Channel Mode

    59, for the exact procedure. 4. Wait until the blade has completely booted and is up and running. 5. Remove the blade from the system again. Installing and Removing the Blade on page 59, for the exact procedure. ATCA-7475 Installation and Use (6806800S38D)

  • Page 101: Ipmi Support

    BIOS 6. Set switch SW4-3 and SW4-4 to OFF. Now the BIOS default settings are restored. IPMI Support The ATCA-7475 BIOS provides the following IPMI support: Sets initial timestamp for IPMI SEL events.  Sends a Boot Initiated event ...

  • Page 102: Bios Error Logging

    Memory event 'Correctable ECC logging limit reached'. No further correctable errors are logged for this DIMM. Table 4-17 Logged Error Events Error SMIBIOS IPMI Correctable: Single-bit ECC memory error Sensor: Memory, Offset 00h - Correctable ECC Memory Error ATCA-7475 Installation and Use (6806800S38D)
  • Page 103 Multi-bit ECC memory error Sensor: Memory, Offset 01h - Uncorrectable ECC Memory Error PCI PERR PCI Parity Error Sensor: Critical Interrupt, Offset 04h PCI PERR PCI SERR PCI System Error Sensor: Critical Interrupt, Offset 05h PCI SERR ATCA-7475 Installation and Use (6806800S38D)

  • Page 104: Ipmi Error Logging

    03h Secondary processor initialization 04h User authentication 05h User-initiated system setup 06h USB configuration 07h PCI configuration 08h Option ROM initialization 09h Video initialization 0Ah Cache initialization 0Ch Console input initialization 13h Starting Operating System ATCA-7475 Installation and Use (6806800S38D)
  • Page 105 Fh DIMM number unknown DIMM number per Channel 0..1 DIMM channel 0..2 CPU Socket 0..1 See naming convention for DIMM: Figure "ATCA-7475 Blade Layout" on page Critical Interrupt (13h) Offset 04h PCI PERR Offset 05h PCI SERR Event Data2: Bus number...

  • Page 106: Smbios Error Logging

    DMI structure System Event Log Type 15. The DMI table can be read by the Linux tool dmidecode. The "Log Change Token" in SMBIOS Type 15 structure is not supported. The following SMBIOS Events are supported: Single-bit ECC memory error  Multi-bit ECC memory error  ATCA-7475 Installation and Use (6806800S38D)

  • Page 107: Single-Bit Ecc Memory Error

    BYTE These fields contain the BCD representation of the date and time 08h-0Bh Memory Information UINT32 OEM extension Table 4-20 Memory Information Definition Description reserved 8-15 DIMM number per Channel 0..1 16-23 DIMM channel 0..2 ATCA-7475 Installation and Use (6806800S38D)

  • Page 108: Multi-Bit Ecc Memory Error

    DIMM channel 0..2 24-31 CPU Socket 0..1 4.11.3.3 POST Error If an error has occurred during the BIOS phase, a POST Error event is generated. There is only one POST Error event per boot generated. ATCA-7475 Installation and Use (6806800S38D)

  • Page 109: Table 4-23 Post Error Event Format

    OEM: IPMI failure OEM: IPMI Boot Parameter read/write error OEM: IPMI Boot Parameter checksum error OEM: IPMI Boot Parameter locked Table 4-25 Result Second DWORD supported POST Errors Description OEM: unspecified error OEM: North Bridge error ATCA-7475 Installation and Use (6806800S38D)

  • Page 110: Pci Parity Error

    Name Format Description Event Type BYTE Event Type = 09h Length BYTE always 0Ch 02h-07h Date/Time Fields BYTE These fields contain the BCD representation of the date and time 08h-0Bh PCI Information UINT32 OEM extension ATCA-7475 Installation and Use (6806800S38D)

  • Page 111: Pci System Error

    BYTE These fields contain the BCD representation of the date and time 08h-0Bh PCI Information UINT32 OEM extension Table 4-29 Memory Information Definition Description reserved 8-15 PCI Function 16-23 PCI Device 24-31 PCI Bus number ATCA-7475 Installation and Use (6806800S38D)

  • Page 112: Cpu Failure

    These fields contain the BCD representation of the date and time 08h-0Bh Memory Information UINT32 OEM extension Table 4-32 Memory Information Definition Description reserved 8-15 DIMM number per Channel 0..1 16-23 DIMM channel 0..2 24-31 CPU Socket 0..1 ATCA-7475 Installation and Use (6806800S38D)

  • Page 113: Log Area Reset/Cleared

    U3 are set to red. Shortly before closing BIOS and starting an operation system, U3 is switched off. 4.13 Upgrading the BIOS A BIOS upgrade kit for the blade is available. This allows the BIOS to be upgraded. The ATCA-7475 Installation and Use (6806800S38D)

  • Page 114: Bios Status Codes

    Table 4-35 BIOS Status Codes POST Code Description 0x01 Power On Post Code 0x02 Early Microcode Load 0x03 Enable Cache 0x06 Early CPU Init 0x20 SMI Init DXE 0x21 ACPI Support 0x22 APCI Table Init ATCA-7475 Installation and Use (6806800S38D)
  • Page 115 0x3F Firmware Find PEI 0x41 Flash Communication DXE/SMM 0x45 Hard Disk Password 0x46 Hii Database Init 0x47 Form Browser Core DXE 0x48 Form Browser Simple Text View Layout 0x49 Form Browser Simple Text View DXE ATCA-7475 Installation and Use (6806800S38D)
  • Page 116 SCSI OPROM Pass Thru DXE 0x6B CRC32 Section Extract DXE 0x6D Flash Hob PEI / Trap SMM 0x70 Security Stub DXE 0x71 Serial Terminal Init 0x72 Setup Init 0x73 SMBIOS Init 0x74 SMBIOS Event Log ATCA-7475 Installation and Use (6806800S38D)
  • Page 117 PCH Flash Controller 0xA0 Platform Init Stage 0 0xA1 Platform Init Stage 1 0xA3 Platform Init DXE 0xA4 S3 Save 0xA5 Platform Flash DXE/SMM 0xA6 Platform SMM 0xA9 Platform Setup Advanced Init 0xAA Platform Setup ATCA-7475 Installation and Use (6806800S38D)
  • Page 118 Memory Initialization: JEDEC Init 0xB7 Memory Initialization: Channel Training 0xB8 Memory Initialization: Throttling Init 0xB9 Memory Initialization: BIST 0xBA Memory Initialization: Init 0xBB Memory Initialization: DDR Memory Mapping 0xBC Memory Initialization: RAS Configuration 0xBF Memory Initialization: MRC Done ATCA-7475 Installation and Use (6806800S38D)
  • Page 119 Entering DXE IPL normal Boot Path 0xF5 Entering DXE IPL S3 Boot Path 0xF6 Exiting S3 boot path back to the OS 0xF7 Entering DXE IPL recovery boot path 0xF8 Exiting DXE IPL to enter DXE phase ATCA-7475 Installation and Use (6806800S38D)
  • Page 120 No Memory found at the end of PEI 0xFC No DXE IPL found at the end of PEI 0xFD No DXE found at the end of IPL 0xFE No PPIs found by DXE 0xFF Missing arch protocols at the end of DXE ATCA-7475 Installation and Use (6806800S38D)

  • Page 121: Functional Description

    Chapter 5 Functional Description Block Diagram The block diagram shows how the devices work together and the data paths used. Figure 5-1 Block Diagram ATCA-7475 1866 1866 V2 10 V2 10 ATCA-7475 Installation and Use (6806800S38D)

  • Page 122: Processor

    ATCA-7475 provides one DIMM slot per memory channel and thus a 1DPC (DIMM per channel configuration). Use of 2-rank DIMM is essential in this configuration to have the best data bandwidth throughput.

  • Page 123: Platform Controller Hub (Pch)

    Mixing of Standard Voltage and LVDDR3 is possible and results in all DIMMs running at Standard Voltage. ATCA-7475 supports Low voltage LVDDR3 Memory which can work at Standard Voltage 1.5 and reduced Voltage of 1.35 V. You can use LVDDR3 to reduce power consumption and improve the thermal performance of the blade.

  • Page 124: Pch I/O Controller Features

    Management Engine Power Management support. High Precision Event Timers (HPET)  System TCO (total cost of ownership) Reduction circuits  SMBus Host controller (D31:F3) and SMLINK1 interface for access from external Host.  General purpose I/O pins (D31:F0)  ATCA-7475 Installation and Use (6806800S38D)

  • Page 125: Pch Intel Quickassist And Quad Mac Pcie Endpoint

    Functional Description 5.4.2 PCH Intel QuickAssist and Quad MAC PCIe Endpoint The PCHs four 1Gb Ethernet MACs are used on ATCA-7475 to provide the Dual AdvancedTCA Base Interface 10/100/1000Base-T  provide two Faceplate 10/100/1000Base-T interfaces  The PCH Intel QuickAssist Technology supports following features in Hardware and through a...

  • Page 126: Firmware Flashes

    The following figure shows the I/O functions provided by Intel Cavecreek PCH and those used on ATCA-7475. Figure 5-2 Intel Cavecreek PCH on ATCA-7475 Block Diagram Firmware Flashes The Blade has two physically separate 8 MB flash devices hosting the BIOS firmware: Primary (or Default BIOS) Flash (SPI 0) ...

  • Page 127: Ethernet Ports

    Functional Description The flash is allocated for storing the binary code of the BIOS. The ATCA-7475 boots from the primary flash SPI 0 under normal circumstances. If booting BIOS from primary flash SPI 0 fails, a hardware mechanism automatically changes the flash device select logic to boot from the recovery flashSPI 1.

  • Page 128: Marvel Switch Initialization

    Specific Interrupt PHY Register Page 0 Register 18, Bit 10 Link Status Changed Interrupt Enable. PHY Port 0,1 Led0 configured for Mode 000 (On-Link, Off-No Link) PHY Register Page 3 Register 16 Bits 3:0, LED Function Control Register. ATCA-7475 Installation and Use (6806800S38D)

  • Page 129: Storage Controller

    The Sata interface is compliant to SATA 3Gb/s speed. BIOS ATCA-7475 provides a BIOS firmware that is stored in flash memory. It can be updated remotely via Ethernet or locally via operating system. Along with the BIOS and BIOS Setup program, the flash memory contains POST and Plug and Play support.

  • Page 130: Serial Redirection

    Alternatively to the CPU serial console, the IPMC serial console is also available on the face plate serial connector. It can be selected via specific IPMI OEM command. ATCA-7475 Installation and Use (6806800S38D)

  • Page 131: Serial Over Lan

    5.14 Front Board Face Plate The blade's face plate provides the following interfaces and control elements: Two USB 2.0 ports  Two 10/1000/1000Base-T Ethernet ports  ATCA-7475 Installation and Use (6806800S38D)

  • Page 132: Faceplate Serial Interfaces

    5.15 Faceplate Serial Interfaces The ATCA-7475 has two serial interfaces. They are fully compliant to industry standard 16550 asynchronous communication controllers. The two Serial line interfaces #1 and #2 are integrated in the Intel DH8900CC PCH and routed to the onboard FPGA, which distributes them to either Faceplate, RTM, or IPMC for SOL.

  • Page 133: Ipmc Debug Console

    The IPMC Debug Console IF connection is normally routed to a 3-pin onboard header (RS232) The IPMC Debug monitor terminal output can also be routed to the Faceplate. The IPMC Debug Console is also available when the ATCA-7475 Payload is powered off. Table 5-3 IPMC Debug Console Destination Selection...

  • Page 134: Real Time Clock

    CPUs of the ATCA-7475. Each Intel DH8920CC connects with a x16 PCIe Gen2 interface to each Xeon E5-2600 V2 CPU on the ATCA-7475. The purpose of the Acceleration module is to provide two additional Next Generation Communications Platform Controller hubs with their respective QuickAssist technology coprocessors.

  • Page 135: Smbus

    Additionally both CPUs provide 2x SMBuses to connect to the SPD PROMs of the DDR3 memory system. Two I2C Bus Level Translators of type PCA9517A are used for voltage level translation to buffer the SMBus portion going to the SPD PROMs on the DIMM. ATCA-7475 Installation and Use (6806800S38D)

  • Page 136: Table 5-6 Smbus Address Map

    Functional Description The following figure shows the ATCA-7475 SMBus architecture. Figure 5-4 SMBus Architecture Table 5-6 SMBus Address Map Device Name Device Type Location SMBus Controller Address SPD EEPROM 24C02 CPU0 CH 0 (A) DIMM#1 CPU#0 SMB: AB 1010.000x b=A0...
  • Page 137 SMBUSID option is 0xC0) MAX6618 PECI MAX6618 Base Board Intel DH8900CC 0x54 IDPROM 24C02 Accelerator Module Intel DH8900CC Mellanox FAB-IF MAC- Base Board Intel DH8900CC MT27514 #1 Mellanox FAB-IF MAC- Base Board Intel DH8900CC MT27514 #2 ATCA-7475 Installation and Use (6806800S38D)
  • Page 138 Functional Description ATCA-7475 Installation and Use (6806800S38D)

  • Page 139: Maps And Registers

    Maps and Registers Interrupt Structure The ATCA-7475 supports NON-APIC (legacy PIC Mode) and APIC mode of Interrupt delivery to the CPUs. 8259 PIC mode interrupt concentrator inside the Intel Cavecreek PCH supports 16 interrupts (8 external signal inputs). The IO-APIC device inside the Intel Cavecreek PCH supports 24 interrupt sources.

  • Page 140: Intel Dh8900Cc Pch Non-Apic (Pic Mode) D31:F0 Interrupt Mapping

    FERR# assertion. May optionally be used for SCI or TCO interrupt if FERR# not needed. SATA SATA Primary (legacy mode), or via SERIRQ or PIRQ# SATA SATA Secondary (legacy mode), or via SERIRQ or PIRQ# ATCA-7475 Installation and Use (6806800S38D)

  • Page 141: Intel Cavecreek Pch Dh8900Cc Apic (D31:F0) Interrupt Mapping

    Internal devices are routable PIRQB# PIRQ[B]# Internal devices are routable PIRQC# PIRQ[C]# Internal devices are routable PIRQD# PIRQ[D]# Internal devices are routable PIRQ[E]# Option for SCI, TCO, and HPET #0,1,2,3. For other internal devices are routable. ATCA-7475 Installation and Use (6806800S38D)

  • Page 142: Nmi Generation

    SERR# signal, or via message from EP due to memory ECC errors can instead be SandyBridge-EP routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11). ATCA-7475 Installation and Use (6806800S38D)

  • Page 143: Fpga Registers

    Maps and Registers FPGA Registers The programmable logic required on ATCA-7475 resides in an FPGA. It implements special functions as follows: LPC Bus Interface  SPI interface connected to IPMC and SPI bit-stream flashes  Reset controller  Interrupt Masking, Routing, and support of SERIRQ ...

  • Page 144: Registers

    For register description, the convention shown in Table 1 Register Default and Table 2 Register Access Type are used. Table 6-4 Register Default Default Description Not applicable or undefined 0 or 1 Default value after PWR_GOOD is valid or after PCH_PLTRST_ deassertion. Undef. Undefined value ATCA-7475 Installation and Use (6806800S38D)

  • Page 145: Register Decoding

    The FPGA registers can be accessed from the host or the IPMC. For the host access, LPC bus interface is used. The IPMC uses an SPI interface. 6.3.1.1 LPC Decoding The LPC bus supports different protocols. ATCA-7475 Installation and Use (6806800S38D)

  • Page 146: Spi Register Decoding

    The FPGA provides an 8 bit wide register to store POST codes to the LPC I/O address 0x80. The two nibbles of the register are converted to 7 segment codes and are displayed as two hex values by two 7 segment LED Displays. ATCA-7475 Installation and Use (6806800S38D)

  • Page 147: Table 6-8 Post Code Register

    The IPMC can read the POST code using the SPI interface (with the signal IPMC_SPI_SS_FPGA_ asserted) and the SPI address 0x7F. Table 6-8 POST Code Register LPC I/O Address: 0x80 IPMC SPI Address: 0x7f Description Default Access POST codes from host LPC: r/w IPMC: r ATCA-7475 Installation and Use (6806800S38D)

  • Page 148: Fpga Register Mapping

    Module Identification Register 0x01 FPGA Version Register 0x02 Reserved / Not used 0x03 Serial Redirection Control Register 0x04 SOL Control Register 0x05 Serial Line Routing Registers 0x06 Reserved 0x07 Reserved 0x08 RTM SPI Address/Command Register ATCA-7475 Installation and Use (6806800S38D)
  • Page 149 CPU 0 PCI Express Hot Plug I2C IO Expander Registers 0x38-0x3F CPU1 PCI Express Hot Plug I2C IO Expander Registers 0x40 Flash Status Register 0x41 - 0x42 Boot Flash Write Enable Registers 0x43 BIOS Boot Mode Register ATCA-7475 Installation and Use (6806800S38D)

  • Page 150: Table

    Reserved / Not used 0x7A - 0x7C IPMC - BIOS Communication Registers 0x7D LPC Scratch Register. 0x7E IPMC Scratch Register. 0x7F POST codes from host 1. For LPC I/O accesses add the LPC I/O Base Address 0x600 ATCA-7475 Installation and Use (6806800S38D)

  • Page 151: Module Identification Register

    Maps and Registers 6.4.3 Module Identification Register The Module Identification Register identifies the ATCA-7475. Table 6-10 Module Identification Register Address Offset: 0x00 Description Default Access ATCA-7475 Module Identification 0x70 6.4.4 Version Register The version register provides the version of the FPGA bit stream. The initial value starts at 0x06 with Revision B and is incremented with each new release.

  • Page 152: Serial Over Lan (Sol) Control Register

    PWR_GOOD: 0 LPC: r/w 0: disabled IPMC: r 1: enabled. COM1 is forwarded to IMPC SOL over COM2 enable: PWR_GOOD: 0 LPC: r/w 0: disabled IPMC: r 1: enabled. COM2 is forwarded to IMPC Reserved ATCA-7475 Installation and Use (6806800S38D)

  • Page 153: Serial Line Routing Register

    SPI master protocol. The signal RTM_SPI_MISO is also used to signal an ARTM interrupt to the base board. See RTM Interrupt Status Register on page 164. Note: At the moment there is no ARTM with an SPI interface defined. ATCA-7475 Installation and Use (6806800S38D)

  • Page 154: Table 6-15 Rtm Spi Address/Command Register

    A write access to the RTM SPI Address/Command Register with the Command Bit 1 (Read) starts an SPI read transaction. This contains the data read from the SPI device. Table 6-17 RTM SPI Read Register Address Offset: 0x09 Description Default Access RTM SPI read data LPC: r ATCA-7475 Installation and Use (6806800S38D)

  • Page 155: Dimm Adr Status Register

    The same situation occurs, if two reset sources go active at the same time. OS should never write to this register. ATCA-7475 Installation and Use (6806800S38D)

  • Page 156: Reset Mask Register

    CPU. 1 in the register bit indicates that the associated reset is enabled. 0 indicates that the associated reset source is masked. Table 6-20 Reset Mask Register Address Offset: 0x11 Description Default Access Reserved ATCA-7475 Installation and Use (6806800S38D)

  • Page 157: Bios Ipmc Watchdog Timeout Register

    Table 6-21 BIOS IPMC Watchdog Timeout Register Address Offset: 0x12 Description Default Access BIOS IPMC Watchdog Timeout: PWR_GOOD:0 LPC: r/w1c 1: IPMC Watchdog Timeout occurred IPMC: r BIOS IPMC Pre-Timeout PWR_GOOD:0 LPC: r/w1c 1: IPMC Pre-Timeout occurred IPMC: r Reserved ATCA-7475 Installation and Use (6806800S38D)

  • Page 158: Bios Push Button Enable Register

    This occurs if two reset sources go active at the same time. BIOS should never write to this register. ATCA-7475 Installation and Use (6806800S38D)

  • Page 159: Os Ipmc Watchdog Timeout Register

    When one of the IPMC Watchdog Timeout bit of IPMC Watchdog Timeout Register is set, the corresponding OS IPMC Watchdog Timeout Register bit is set. The OS clears this status bit by writing 1. BIOS should never write to this register. ATCA-7475 Installation and Use (6806800S38D)

  • Page 160: Ipmc Watchdog Timeout Register

    Address Offset: 0x16 Description Default Access IPMC Watchdog Timeout: PWR_GOOD:0 IPMC: r/w 0: No IPMC Watchdog Timeout 1: IPMC Watchdog Timeout occurred IPMC Pre-Timeout PWR_GOOD:0 IPMC: r/w 0: No IPMC Pre-Timeout 1: IPMC Pre-Timeout occurred Reserved ATCA-7475 Installation and Use (6806800S38D)

  • Page 161: Ipmc Reset Source Register

    PWR_GOOD:0 IPMC: r/w1c 1: Reset occurred INTEL_INIT3V3_ PCH output PWR_GOOD:0 IPMC: r/w1c 1: Event Occurred PCH_PLTRST_ reset PWR_GOOD:0 IPMC: r/w1c 1: Reset occurred IPMC_RST_ REQ_ Payload Reset from IPMC. PWR_GOOD:0 IPMC: r/w1c 1: Reset occurred ATCA-7475 Installation and Use (6806800S38D)

  • Page 162: Dimm Adr Configuration Register

    0: ADR disabled ADR enable for watchdog reset PWR_GOOD:0 LPC: r/w PCH_WDT_TOUT_ IPMC: r/w 1: ADR enabled 0: ADR disabled ADR enable for software reset PWR_GOOD:0 LPC: r/w 1: ADR enabled IPMC: r/w 0: ADR disabled Reserved ATCA-7475 Installation and Use (6806800S38D)

  • Page 163: 10Software Reset Register

    The interrupt status registers indicate the status of the interrupt input signals. They are read only registers. When an interrupt is active the corresponding status bit is read 1. Write access to these register bits does not have any impact. ATCA-7475 Installation and Use (6806800S38D)

  • Page 164: Rtm Interrupt Status Register

    1: RTM_SPI_MISO is low. One or more RTM interrupt sources are active. When RTM SPI Master face is active the current level is latched 1. When an interrupt is active, the corresponding status bit is read 1. ATCA-7475 Installation and Use (6806800S38D)

  • Page 165: Processor Hot Status Register

    Address Offset: 0x22 Description Default Access Telecom CLK_MONITOR_FINISHED interrupt Event 0: LPC: r One or more Telecom Clock measurements have finished. Telecom CLK_MONITOR_OUT_OF_RANGE interrupt LPC: r Event 1: One or more Telecom Clocks are out of range. ATCA-7475 Installation and Use (6806800S38D)

  • Page 166: Interrupt Mask And Map Registers

    Interrupt input from payload Temp sensor 0x24 ETH_BASE_INT_ IRQ request from 88E6161 Marvell Switch 0x25 ETH_FP_INT_ IRQ request from 88E1322 Marvell PHY 0x26 THERM_ALERT_ IRQ request from IOH Thermo-sensor 0x27 APB_ALARM An 48V input alarm (low voltage, etc) 0x28 ATCA-7475 Installation and Use (6806800S38D)
  • Page 167 Link status of the Base interface #1 0x29 BASEIF2_LINKLOSS Link status of the Base interface #2 0x2A CPU0_PRCHT_ CPU0 Processor hot interrupt 0x2B CPU1_PRCHT_ CPU1 Processor hot interrupt 0x2C Telecom Interrupt Telecom Interrupt. Not implemented 0x2D RTM_SPI_MISO RTM interrupt sources 0x2E ATCA-7475 Installation and Use (6806800S38D)

  • Page 168: Table

    0x11: Frame number 17. IOCHK_ 0x12: Frame number 18. INTA_ 0x13: Frame number 19. INTB_ 0x14: Frame number 20. INTC_ 0x15: Frame number 21. INTD_ 0x16 - 0x1F: Frame number 22-31. IRQ Frame Number not valid. Value is ignored. ATCA-7475 Installation and Use (6806800S38D)

  • Page 169: Base Interface Link Interrupt Status Register

    6.4.12 PCI Express Hot Plug I2C IO Expander Registers Each CPU supports four PCI Express Hot Plug ports. The Hot Plug registers for CPU0 are mapped to 0x30 to 0x37 and the registers for CPU 1 are mapped to 0x38 - 0x3F. ATCA-7475 Installation and Use (6806800S38D)

  • Page 170: Hot-Plug Virtual Pin Port Registers

    Input signal that indicates if a hot IPMC: r/w pluggable PCI Express card/module is LPC: r currently plugged into the slot. PWRFLT# Input Input signal from the power controller to indicate that a power fault has occurred. ATCA-7475 Installation and Use (6806800S38D)
  • Page 171 The FPGA emulates the CPA9555 device. Each CPU has two devices attached to the corresponding I2C bus (SMBus). The I2C slave addresses are 0x20 for the first device and 0x21 for the second device. ATCA-7475 Installation and Use (6806800S38D)

  • Page 172: Pca9555 Internal Register Access

    Table 6-38 Content of PCA9555 Internal Register Address Offset: CPU0 Device1 (Slave address 0x20): 0x35 CPU0 Device2 (Slave address 0x21): 0x37 CPU1 Device1 (Slave address 0x20): 0x3D CPU1 Device1 (Slave address 0x21): 0x3F Description Default Access Content of PCA9555 register ATCA-7475 Installation and Use (6806800S38D)

  • Page 173: Flash Status And Protection Registers

    0: Selects Default Boot SPI Flash. 1: SW3.2 ON 1: Selects Recover Boot SPI Flash. IPMC signal BOOT_SELECT. Boot Flash Select. Ext. LPC: r 0: Selects Default Boot SPI Flash 1: Selects Recovery Boot SPI Flash ATCA-7475 Installation and Use (6806800S38D)

  • Page 174: Table 6-40 Default Boot Spi Flash Write Enable

    Boot Block. Table 6-41 Recovery Boot SPI Flash Write Enable Address Offset: 0x42 Description Default Access Recovery Boot SPI Flash enable/disable. LPC: w A write value 0xC3 enables the Flash. All other values disables the Flash. ATCA-7475 Installation and Use (6806800S38D)

  • Page 175: Bios Boot Mode Register

    1: UC1_EQ_RX is tri-state Control output Signal UC1_EQ_TX: LPC: r/w 0: UC1_EQ_TX is driven low IPMC: r 1: UC1_EQ_TX is tri-state Control output Signal UC2_EQ_RX: LPC: r/w 0: UC2_EQ_RX is driven low IPMC: r 1: UC2_EQ_RX is tri-state ATCA-7475 Installation and Use (6806800S38D)

  • Page 176: Ipmc E-Keying Status Register

    1: UC4_EQ_TX is tri-state 6.4.16 IPMC E-Keying Status Register Table 6-44 IPMC E-Keying Status Register Address Offset: 0x49 Description Default Access IPMC_UPDCH_[4:0]. IPMC electronic key signals. Ext. LPC: r IPMC_FAB1_10G_SEL_ Ext. LPC: r IPMC_FAB2_10G_SEL_ Ext. LPC: r Reserved ATCA-7475 Installation and Use (6806800S38D)

  • Page 177: Ipmc E-Keying Control Register

    Control red LED output Signal LED_RED_: LPC: r/w 0: LED_RED_ is driven high IPMC: r 1: LED_RED_ is driven low Control user LED output Signal LED_USER1_: LPC: r/w 0: LED_USER1_ is driven high IPMC: r 1: LED_USER1 is driven low ATCA-7475 Installation and Use (6806800S38D)

  • Page 178: Cpld Revision Register

    CPLD Version. The CPLD uses the signals Ext. CPLD_REV_BIT[2:0]. Reserved 6.4.20 Spare Signals Status Registers Table 6-48 Spare Signal Status Register Address Offset: 0x52 Description Default Access Reserved Signal level of CPLD_SPARE Signal level of SH7757_2_FPGA_BMCRSVD<0> Signal level of SH7757_2_FPGA_BMCRSVD<1> ATCA-7475 Installation and Use (6806800S38D)

  • Page 179: Dimm Event Register

    Shows the status of DIMM Event signal from CPU1 Channel 1/F Ext. Shows the status of DIMM Event signal from CPU1 Channel 2/G Ext. Shows the status of DIMM Event signal from CPU1 Channel 3/H Ext. ATCA-7475 Installation and Use (6806800S38D)

  • Page 180: Cpu Type And Presence Detection Register

    6.4.23 Memory Temperature Status Register Table 6-51 Memory Temperature Status Register Address Offset: 0x55 Description Default Access Represents the temperature status of CPU0 memory channel 0,1 Ext. 0: Temperature threshold crossed 1: Normal working temperature ATCA-7475 Installation and Use (6806800S38D)

  • Page 181: Base Interface Link Status Signals Register

    This register reflects the actual status of the external BASEIFx_LINKLOSS signals. Table 6-52 Base Interface Link Status Signals Register Address Offset: 0x56 Description Default Access Base interface 1 link status (Status of BASEIF1_LINKLOSS signal) Ext. 0:Link established 1:Link is down ATCA-7475 Installation and Use (6806800S38D)

  • Page 182: Miscellaneous Status/Control Registers

    0: FPGA connected to recovery PROM 1: FPGA connected to default PROM IPMC_GPIO1 GPIO1 signal from IPMC Ext. ACC_MOD_PRSNT_ ACC module present signal Ext. 0: ACC module not present. Signal high. 1: ACC module present. Signal low. ATCA-7475 Installation and Use (6806800S38D)

  • Page 183: Telecom Clock Control And Supervision Registers

    Triggers 16 SPI clocks and shifts the address out to MOSI. The Data on MISO is shifted in. Table 6-55 ACS8225B SPI Status Register Address Offset: 0x5D Description Default Access ACS8825B SPI Address (max 128 bytes) CPU_PWROK: 0 ATCA-7475 Installation and Use (6806800S38D)

  • Page 184: Table 6-56 Acs8225B Spi Access Data Register

    Description Default Access Control ACS SRCSW signal: CPU_PWROK: 0 LPC: r/w 0: drive LCCB_SRCSW low 1: drive LCCB_SRCSW high Control ACS_PORST# signal: LPC: w1c 0: No action 1: drive LCCB_RST_ low for one clock cycle ATCA-7475 Installation and Use (6806800S38D)

  • Page 185: Telecom Clock Enable And Routing Register

    Select clock source for signal LCCB_SYSCLK_OUT_A PWR_GOOD: 0 LPC: r/w 00: LCCB_SYSCLK_IN_A 01: LCCB_SYSCLK_IN_B 10: LCCB_FPETH_RCLK1 11: LCCB_FPETH_RCLK1 Select clock source for signal LCCB_SYSCLK_OUT_B PWR_GOOD: 0 LPC: r/w 00: LCCB_SYSCLK_IN_A 01: LCCB_SYSCLK_IN_B 10: LCCB_FPETH_RCLK1 11: LCCB_FPETH_RCLK1 ATCA-7475 Installation and Use (6806800S38D)

  • Page 186: Telecom Clock Monitor Registers

    Table 6-61 Telecom Clock Monitor Status Register Address: 0x62 Description Default Access Result available for supervised Telecom Clock 0 to 4. LPC: r/w1c Corresponding bit is set when measurement has finished. Clearing bit triggers new measurement. ATCA-7475 Installation and Use (6806800S38D)

  • Page 187: Table 6-62 Telecom Clock Monitor Out Of Range Register

    Reserved Table 6-63 Telecom Clock Monitor Select Register Address: 0x64 Description Default Access Select supervised Telecom Clocks. See Table "Supervised Telecom LPC: r/w Clocks Reference List" on page 186. 0-4: Select corresponding clock 5-7: Reserved ATCA-7475 Installation and Use (6806800S38D)

  • Page 188: Table 6-64 Telecom Clock Monitor Time Base Register

    12: Gate is open for 1024ms 13: Gate is open for 2048ms 14: Gate is open for 4096ms 15: Gate is open for 8192ms 16: Gate is open for 16384ms 17 and all others: Gate is open for 32768ms ATCA-7475 Installation and Use (6806800S38D)
  • Page 189 9 and all others: Period Counter incremented with each 512th master clock Reserved Measurement Mode: LPC: r/w 0: Gate Mode. Count positive clock edges during open gate. 1: Period Mode. Count number of clocks which fit in one period. ATCA-7475 Installation and Use (6806800S38D)

  • Page 190: Table 6-65 Telecom Clock Monitor Frequency/Period Register

    Table 6-67 Telecom Clock Monitor Upper Limit Register Address: 0x6E -0x6F Description Default Access 15:0 Upper limit for supervised Telecom Clock: LPC: r/w Used by Table "Telecom Clock Monitor Out of Range Register" on page 187. ATCA-7475 Installation and Use (6806800S38D)

  • Page 191: Serial Management Interface (Mii) Control Registers

    Turnaround status bit. The bit is set/reset after a MDIO read LPC: operation. r/w1c 0: A target device has driven MDIO low during 2nd TA bit (normal operation) 1: No device has responded to the read operation ATCA-7475 Installation and Use (6806800S38D)

  • Page 192: Table 6-70 Mii Management Interface Lower Byte Register

    Table 6-70 MII Management Interface Lower Byte Register Address Offset: 0x72 Description Default Access Lower Data Byte LPC: r/w Table 6-71 MII Management Interface Upper Byte Register Address Offset: 0x73 Description Default Access Upper Data Byte LPC: r/w ATCA-7475 Installation and Use (6806800S38D)

  • Page 193: Scratch Registers

    Table 6-74 IPMC BIOS Communication Register 3 Address Offset: 0x7C Description Default Access IPMC BIOS PWR_GOOD:0 LPC: r/w Communication bits IPMC: r/w Table 6-75 LPC Scratch Register Address Offset: 0x7D Description Default Access LPC Scratch bits PWR_GOOD:0 LPC: r/w IPMC: r ATCA-7475 Installation and Use (6806800S38D)

  • Page 194: Table 6-76 Ipmc Scratch Register

    Maps and Registers Table 6-76 IPMC Scratch Register Address Offset: 0x7E Description Default Access IPMC Scratch bits PWR_GOOD:0 IPMC: r/w LPC: r ATCA-7475 Installation and Use (6806800S38D)

  • Page 195: Serial Over Lan

    Installing the ipmitool You can download the open source tool ipmitool from http://ipmitool.sourceforge.net (at the time of publishing this manual the current version is 1.8.11). Documentation for this tool is also freely available on this site. ATCA-7475 Installation and Use (6806800S38D)

  • Page 196: Configuring Sol Parameters

    You can use standard IPMI commands or the ipmitool to modify the parameters. 7.3.1 Using Standard IPMI Commands This example shows how to setup the SOL configuration parameter with standard IPMI commands. Ipmicmd is used on the local IPMC and the IP is configured. ATCA-7475 Installation and Use (6806800S38D)

  • Page 197: Using Ipmitool

    SOL session for base 0 (channel 1) and base 1 (channel 2): root@localhost:~# ipmitool lan print 1 Set in Progress : Set Complete Auth Type Support Auth Type Enable : Callback : : User : Operator : : Admin ATCA-7475 Installation and Use (6806800S38D)
  • Page 198 : User : Operator : : Admin : OEM IP Address Source : Unspecified IP Address : 172.17.1.220 Subnet Mask : 255.255.0.0 MAC Address : 00:00:00:00:00:00 Default Gateway IP : 172.17.0.1 Default Gateway MAC : 00:00:00:00:00:00 ATCA-7475 Installation and Use (6806800S38D)

  • Page 199: Establishing An Sol Session

    2. Compile and install the ipmitool on your target which is destined for opening the SOL session on the ATCA-7475. For details refer to Installing the ipmitool on page 195. 3. Apply an IP address to the ATCA-7475 SOL interface - for details refer to Configuring SOL Parameters on page 196.
  • Page 200 Serial Over LAN 6. Start ATCA-7475 SOL session on your target with the ipmitool and the configured IP address for the ATCA-7475 SOL interface. ipmitool -C 1 -I lanplus -H 172.16.0.221 -U soluser -P solpasswd -k gkey sol activate For details on the command parameters, refer to the ipmitool documentation available on http://ipmitool.sourceforge.net.

  • Page 201: Boot Bank Selection

    BMC watchdog expires, the IPMI management controller will swap the boot banks before resetting the CPU. Thus, the blade can recover by booting from its redundant boot flash, which contains the old active firmware image, which did work before firmware upgrade. ATCA-7475 Installation and Use (6806800S38D)

  • Page 202: Figure 8-1 Failsafe Mechanism

    Firmware image has a bad checksum  When the Failsafe logic is triggered as a result of the BMC Watchdog timeout, a System Firmware Progress event is logged as follows: Sensor Type: 0x0F (System Firmware Progress) ATCA-7475 Installation and Use (6806800S38D)
  • Page 203 BIOS cannot start and IPMC WDT expired  Aborting FAIL SAFE Mechanism, maximum retries (= 3) are reached.  Payload software is able to detect when failsafe was activated during last boot, for details see Get Feature Configuration on page 228. ATCA-7475 Installation and Use (6806800S38D)

  • Page 204: Glue Logic Fpga Flash Selection

    The IPMI command Set/Get System Boot Options together with the parameter #96 can be used to specify the FPGA boot bank from which the payload shall boot from persistently, for details, see System Boot Options Commands on page 209. ATCA-7475 Installation and Use (6806800S38D)

  • Page 205: Supported Ipmi Commands

    Table 9-2 Supported System Interface Commands Command NetFn (Request/Response) Set BMC Global Enables 0x06/0x07 0x2E Get BMC Global Enables 0x06/0x07 0x2F Clear Message Flags 0x06/0x07 0x30 Get Message Flags 0x06/0x07 0x31 Get Message 0x06/0x07 0x33 Send Message 0x06/0x07 0x34 ATCA-7475 Installation and Use (6806800S38D)

  • Page 206: Watchdog Commands

    2 sensor. The options pre-timeout and power-cycle are not supported. Table 9-3 Supported Watchdog Commands Command NetFn (Request/Response) Reset Watchdog Timer 0x06/0x07 0x22 Set Watchdog Timer 0x06/0x07 0x24 Get Watchdog Timer 0x06/0x07 0x25 ATCA-7475 Installation and Use (6806800S38D)

  • Page 207: Sel Device Commands

    Set SEL Time 0x0A/0x0B 0x49 9.1.5 FRU Inventory Commands Table 9-5 Supported FRU Inventory Commands Command NetFn (Request/Response) Get FRU Inventory Area Info 0x0A/0x0B 0x10 Read FRU Data 0x0A/0x0B 0x11 Write FRU Data 0x0A/0x0B 0x12 ATCA-7475 Installation and Use (6806800S38D)

  • Page 208: Sensor Device Commands

    Get Sensor Event Enable 0x04/0x05 0x29 Get Sensor Event Status 0x04/0x05 0x2B Get Sensor Reading 0x04/0x05 0x2D Get Sensor Type 0x04/0x05 0x2F Set Event Receiver 0x04/0x05 0x00 Get Event Receiver 0x04/0x05 0x01 Platform Event 0x04/0x05 0x02 ATCA-7475 Installation and Use (6806800S38D)

  • Page 209: Chassis Device Commands

    Configurable Boot Property Corresponding Boot Parameter Number Selection between default and backup boot flash as device to boot from Selection between default and backup EEPROM as device where the on-board FPGA loads its configuration stream from ATCA-7475 Installation and Use (6806800S38D)

  • Page 210: Table 9-9 System Boot Options Parameter #96

    BIOS boot parameters as defined in Table 9-15 on page 9.1.7.1.1 System Boot Options Parameter #96 This boot parameter is an Artesyn-specific OEM boot parameter. Its definition is given in the following table. Table 9-9 System Boot Options Parameter #96...

  • Page 211: Table 9-10 System Boot Options Parameter #97

    Supported IPMI Commands 9.1.7.1.2 System Boot Options Parameter #97 This boot parameter is an Artesyn-specific OEM parameter. Its definition is given in the following table. Table 9-10 System Boot Options Parameter #97 Data Byte Description IPMC POST Type Data 1 - Set Selector. This is the processor ID for which the boot option is to be set.

  • Page 212: Table 9-11 System Boot Options Parameter #98

    The default area can only be read by both the IPMI user and the boot firmware. Its purpose is to store factory-programmed default boot options which can be used to restore the standard settings. If you want the boot firmware to read out and use ATCA-7475 Installation and Use (6806800S38D)

  • Page 213: Table 9-12 System Boot Options - Parameter #100 - Data Format

    When reading from the storage area and you find any of these two values, your software should assume that no user-specific boot options have previously been written to the storage area. ATCA-7475 Installation and Use (6806800S38D)

  • Page 214: Table 9-13 System Boot Options Parameter #100 - Set Command Usage

    Depending on the total length of the boot option data, your software may need to write several blocks of 16 bytes in a row, each individually addressed using the block selector. ATCA-7475 Installation and Use (6806800S38D)

  • Page 215: Table 9-14 System Boot Options Parameter #100 - Get Command Usage

    0xC9: Block selector is outside of the allowed range. Reserved. Set to "1". Bit 7: If set to "1", the addressed storage area is locked. Bits 6 ..0: value "100", indicating this OEM boot option command. ATCA-7475 Installation and Use (6806800S38D)

  • Page 216: Table 9-15 System Boot Options Parameter #100 - Supported Parameters

    This is supported by HPI, for details refer to the System Management Interface Based on HPI-B User’s Guide related to your system environment. The following table lists boot parameters which can be configured for the ATCA-7475 blade, using the system boot option parameter #100.

  • Page 217: Table

    Console Redirection after POST on/off usb_legacy USB legacy (DOS) support on/off cpu_ac Number of active Cores per CPU all/1/2/3/4/5/6/7/8/9 cpu_ht Hyperthreading on/off cpu_ed Execution Disable on/off cpu_dca Direct Cache Access on/off cpu_vt Virtualization on/off cpu_ss SpeedStep on/off ATCA-7475 Installation and Use (6806800S38D)

  • Page 218: Table

    Intel IO Virtualization Address on/off Translation Service vtd_ir Intel IO Virtualization Interrupt on/off Remapping vtd_pt Intel IO Virtualization Pass Through on/off sriov PCI Single Root I/O Virtualization on/off usb1 Front Panel USB1 on/off ATCA-7475 Installation and Use (6806800S38D)

  • Page 219: Table 9-16 Boot_Order Devices

    RTM Network 2 rtmnet3 RTM Network 3 rtmnet4 RTM Network 4 rtmnet5 RTM Network 5 rtmnet6 RTM Network 6 usbcdrom USB Cdrom usb1cdrom USB Cdrom connected to USB 1 usb2cdrom USB Cdrom connected to USB 2 ATCA-7475 Installation and Use (6806800S38D)

  • Page 220: Lan Device Commands

    LAN Device Commands Table 9-17 Supported LAN Device Commands Command NetFn (Request/Response) Set LAN Configuration Parameters 0x0C/0x0D 0x01 Get LAN Configuration Parameters 0x0C/0x0D 0x02 Set SOL Configuration Parameters 0x0C/0x0D 0x21 Get SOL Configuration Parameters 0x0C/0x0D 0x22 ATCA-7475 Installation and Use (6806800S38D)

  • Page 221: Picmg 3.0 Commands

    Supported IPMI Commands PICMG 3.0 Commands The Artesyn Embedded Technologies IPMC is a fully compliant AdvancedTCA intelligent Platform Management Controller. It supports all required and mandatory AdvancedTCA commands as defined in the PICMG 3.0 and AMC.0 R2.0 specifications. Table 9-18 Supported PICMG 3.0 Commands...

  • Page 222: Set/Get Power Level

    The blade supports two power levels. In case of a shelf which only allows 200W per slot the P- States of the blade will be restricted to match this requirement. The second power level has no restrictions. For more information, refer to Chapter 4, BIOS, on page ATCA-7475 Installation and Use (6806800S38D)

  • Page 223: Artesyn Embedded Technologies Specific Commands

    Commands The Artesyn Embedded Technologies IPMC supports several commands which are not defined in the IPMI or PICMG 3.0 specification but are introduced by Artesyn Embedded Technologies: serial output commands. Before sending any of these commands, the shelf management software must check ...

  • Page 224: Table 9-20 Request Data Of Set Serial Output Command

    Table 9-20 Request Data of Set Serial Output Command Byte Data Field LSB of Artesyn Embedded Technologies IANA Enterprise number. A value of 0xCD has to be used. Second byte of Artesyn Embedded Technologies IANA Enterprise number. A value of 0x65 has to be used.

  • Page 225: Get Serial Output Command

    Table 9-22 Request Data of Get Serial Output Command Byte Data Field LSB of Artesyn Embedded Technologies IANA Enterprise number. A value of 0xCD has to be used. Second byte of Artesyn Embedded Technologies IANA Enterprise number. A value of 0x65 has to be used.

  • Page 226: Oem Command To Configure Ipmi Features

    Byte Data Field Completion code LSB of Artesyn Embedded Technologies IANA Enterprise number. Second byte of Artesyn Embedded Technologies IANA Enterprise number. MSB of Artesyn Embedded Technologies IANA Enterprise number. Serial output selector 9.3.2 OEM Command to configure IPMI Features...

  • Page 227: Set Feature Configuration

    Table 9-25 Set Feature Configuration Command Byte Data Field Request Data LSB of Artesyn IANA Enterprise Number. A value of CDh shall be used. 2nd byte of Artesyn IANA Enterprise Number. A value of 65h shall be used. MSB of Artesyn IANA Enterprise Number. A value of 00h shall be used.

  • Page 228: Get Feature Configuration

    Table 9-27 Get Feature Configuration Command Byte Data Field Request Data LSB of Artesyn IANA Enterprise Number. A value of CDh shall be used. 2nd byte of Artesyn IANA Enterprise Number. A value of 65h shall be used. MSB of Artesyn IANA Enterprise Number. A value of 00h shall be used.

  • Page 229: Pigeon Point Specific Commands

    Completion Code. Generic plus the following command- specific completion codes: 80h = feature selector not supported. LSB of Artesyn IANA Enterprise Number. A value of CDh shall be used. 2nd byte of Artesyn IANA Enterprise Number. A value of 65h shall be used.
  • Page 230 Table 9-48 on page 246 0x2E/0x2F 0x27 Enable Module Site Table 9-49 on page 248 0x2E/0x2F 0x28 Disable Module Site Table 9-50 on page 248 0x2E/0x2F 0x29 Reset Carrier SDR repository Table 9-51 on page 249 0x2E/0x2F 0x33 ATCA-7475 Installation and Use (6806800S38D)

  • Page 231: Get Status Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7475 Installation and Use (6806800S38D)
  • Page 232 Bits [0:3] Metallic Bus 1 Events These bits indicate pending Metallic Bus 1 requests arrived from the shelf manager: 0: Metallic Bus 1 Query 1: Metallic Bus 1 Release 2: Metallic Bus 1 Force 3: Metallic Bus 1 Free ATCA-7475 Installation and Use (6806800S38D)
  • Page 233 Bits [0:3] Clock Bus 3 Events These bits indicate pending Clock Bus 3 requests arrived from the shelf manager: 0: Clock Bus 3 Query 1: Clock Bus 3 Release 2: Clock Bus 3 Force 3: Clock Bus 3 Free ATCA-7475 Installation and Use (6806800S38D)

  • Page 234: Get Serial Interface Properties Command

    Bits [6:4] Reserved Bits [3:0] Baud Rate ID The baud rate ID defines the interface baud rate as follows: 0: 9600 bps 1: 19200 bps 2: 38400 bps 3: 57600 bps (unsupported) 4: 115200 bps (unsupported) ATCA-7475 Installation and Use (6806800S38D)

  • Page 235: Set Serial Interface Properties Command

    3: 57600 bps (unsupported) 4: 115200 bps (unsupported) Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7475 Installation and Use (6806800S38D)

  • Page 236: Get Debug Level Command

    Bit [1] Low-level Error Logging Enable If set to "1", the IPMC outputs low-level error/diagnostic messages onto the serial debug interface. Bit [0] Error Logging Enable If set to "1", the IPMC outputs error/diagnostic messages onto the serial debug interface. ATCA-7475 Installation and Use (6806800S38D)

  • Page 237: Set Debug Level Command

    Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7475 Installation and Use (6806800S38D)

  • Page 238: Get Hardware Address Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Hardware Address If set to 00, the ability to override the hardware address is disabled. NOTE: A hardware address change only takes effect after an IPMC reset. Response Data Completion Code ATCA-7475 Installation and Use (6806800S38D)

  • Page 239: Get Handle Switch Command

    LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 Handle Switch Status 0x00: The handle switch is open. 0x01: The handle switch is closed. 0x02: The handle switch state is read from hardware. ATCA-7475 Installation and Use (6806800S38D)

  • Page 240: Set Handle Switch Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7475 Installation and Use (6806800S38D)

  • Page 241: Set Payload Communication Time-Out Command

    0.1 to 25.5 seconds. Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7475 Installation and Use (6806800S38D)

  • Page 242: Enable Payload Control Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7475 Installation and Use (6806800S38D)

  • Page 243: Reset Ipmc Command

    Byte Data Field Request Data PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code ATCA-7475 Installation and Use (6806800S38D)

  • Page 244: Graceful Reset Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7475 Installation and Use (6806800S38D)

  • Page 245: Get Payload Shutdown Time-Out Command

    Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 Time-Out measured in hundreds of milliseconds, LSB first ATCA-7475 Installation and Use (6806800S38D)

  • Page 246: Set Payload Shutdown Time-Out Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Module Site ID Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7475 Installation and Use (6806800S38D)
  • Page 247 0: Payload power is bad. 1: Payload power is good. Bit [6] 0: IPMB-L buffer is not attached. 1: IPMB-L buffer is attached. Bit [7] 0: IPMB-L buffer is not ready. 1: IPMB-L buffer is ready. ATCA-7475 Installation and Use (6806800S38D)

  • Page 248: Enable Module Site Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Module Site ID Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7475 Installation and Use (6806800S38D)

  • Page 249: Reset Carrier Sdr Repository Command

    LSB Byte first: byte 1 = 0A, byte 2 = 40, byte 3 = 00 Response Data Completion Code PPS IANA Private Enterprise ID 0x00400A = 16394 (Pigeon Point Systems) LSB Byte first: byte 2 = 0A, byte 3 = 40, byte 4 = 00 ATCA-7475 Installation and Use (6806800S38D)
  • Page 250 Supported IPMI Commands ATCA-7475 Installation and Use (6806800S38D)

  • Page 251: Fru Information And Sensor Data Records

    This multi record area contains the ATCA- area Connectivity Record blade Point to Point Connectivity Record Area according to PICMG 3.0, Rev.1.0. The contents are described in the section 'E- Keying'. Custom usage Min. 256 Byte available ATCA-7475 Installation and Use (6806800S38D)

  • Page 252: Mac Address Fru Oem Records

    FRU Information and Sensor Data Records 10.2 MAC Address FRU OEM Records The Artesyn Embedded Technologies MAC Address record is specified in the following table: Table 10-2 Artesyn ECC MAC Address Record Offset Length Description Record Type ID. A value of C0h (OEM) shall be used for Artesyn ECC OEM records.

  • Page 253: Table 10-4 Interface Type Assignments

    AMC/MicroTCA Common Options Region AMC/MicroTCA Fat Pipe Region AMC/MicroTCA Extended Fat Pipe Region ATCA Update Channel Multi-type (Base, Fabric, and Update channel (or two types of it) are connected to a onboard switch) 11h - FFh reserved ATCA-7475 Installation and Use (6806800S38D)

  • Page 254: Power Configuration

    Hot Swap 0xF0 Refer Table "Sensor Data Records" on page 260. Hotswap_RTM Hot Swap 0xF0 Refer Table "Sensor Data Records" on page 260. Version change Version Change 0x2B Refer Table "Sensor Data Records" on page 260. ATCA-7475 Installation and Use (6806800S38D)
  • Page 255 Refer Table "Sensor Data Records" on page 260. Fw Progress System Firmware Refer Table "Sensor Data Progress 0x0F Records" on page 260. OS Boot OS Boot 0x1F Refer Table "Sensor Data Records" on page 260. ATCA-7475 Installation and Use (6806800S38D)
  • Page 256 Voltage 0x02 Refer Table "Sensor Data Records" on page 260. -48v Amps Current 0x03 Refer Table "Sensor Data Records" on page 260. HoldUp Cap Volts Voltage 0x02 Refer Table "Sensor Data Records" on page 260. ATCA-7475 Installation and Use (6806800S38D)
  • Page 257 Temp 0x01 Refer Table "Sensor Data Records" on page 260. DDR 4 temp Temp 0x01 Refer Table "Sensor Data Records" on page 260. DDR 5 temp Temp 0x01 Refer Table "Sensor Data Records" on page 260. ATCA-7475 Installation and Use (6806800S38D)
  • Page 258 Temp 0x01 Refer Table "Sensor Data Records" on page 260. DDR 7 temp Temp 0x01 Refer Table "Sensor Data Records" on page 260. DDR 8 temp Temp 0x01 Refer Table "Sensor Data Records" on page 260. ATCA-7475 Installation and Use (6806800S38D)

  • Page 259: Figure 10-1 Location Of Temperature Sensors

    FRU Information and Sensor Data Records The following figure shows the locations of all temperature sensors available on-board. Figure 10-1 Location of Temperature Sensors ATCA-7475 Installation and Use (6806800S38D)

  • Page 260: Table 10-7 Sensor Data Records

    0x4: M4 0x5: M5 0x6: M6 0x7: M7 Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold ATCA-7475 Installation and Use (6806800S38D)
  • Page 261 Asrt / Deass Auto 0x02 0x01 Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold ATCA-7475 Installation and Use (6806800S38D)
  • Page 262 0x3: Invalid boot sector 0x4: Timout waiting for user selection Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold ATCA-7475 Installation and Use (6806800S38D)
  • Page 263 Presence discrete 0x1: Entity Absent 0x25 0x6F Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold ATCA-7475 Installation and Use (6806800S38D)
  • Page 264 Asrt / Deass Auto Temp 0x01 0x01 Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold ATCA-7475 Installation and Use (6806800S38D)
  • Page 265 0x5: 1.5V Power Good PCH 0x6: 1.05V Power Good PCH Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold ATCA-7475 Installation and Use (6806800S38D)
  • Page 266 Asrt / Deass Auto 0x01 0x01 Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold ATCA-7475 Installation and Use (6806800S38D)
  • Page 267 Asrt / Deass Auto 0x01 0x01 Asrt: Assertion Unr: Upper non-recoverable threshold Uc: Upper critical threshold Unc: Upper non-critical threshold Deass: Deassertion Lnr: Lower non-recoverable threshold Lc: Lower critical threshold Lnc: Lower non-critical threshold ATCA-7475 Installation and Use (6806800S38D)
  • Page 268 FRU Information and Sensor Data Records ATCA-7475 Installation and Use (6806800S38D)

  • Page 269: Firmware Upgrade

    11.1 HPM.1 Firmware Upgrade 11.1.1 Overview The primary update mechanism for the ATCA-7475 blades is the FCU tool which is delivered with the BBS package for the board. However, the ATCA-7475 board family also supports upgrade of the firmware with the HPM.1 specification. Upgradeable components of the board include the BIOS flash, FPGA flash, and IPMC flash.

  • Page 270: Interface

    The IPMI over LAN interface uses the BASE Ethernet controller to do firmware upgrades. The interface has to be configured before the first use. Configuring this interface is described in Chapter 7, Configuring SOL Parameters, on page 196. Example: ATCA-7475 Installation and Use (6806800S38D)

  • Page 271: Ipmc Upgrade

    If the active firmware failed or is invalid, the Boot loader will switch to the backup partition. When switching, the partitions change their roles. Switching of the partitions also takes place when the firmware is upgraded and activated using the HPM.1 upgrade procedure. ATCA-7475 Installation and Use (6806800S38D)

  • Page 272: Bios/Fpga Upgrade

    11.3 BIOS/FPGA Upgrade Both components (BIOS and FPGA) have two independent boot banks. The switching of this boot banks is not supported by HPM commands of ATCA-7475. Both BIOS/FPGA boot banks can be updated with HPM.1. The BIOS/FPGA upgrade is not fully HPM.1 compatible due to the fact that payload update of this device must also be possible.

  • Page 273: Upgrade Package

    A power cycle is required after the BIOS/FPGA update. 11.4 Upgrade Package The HPM upgrade package for this release contains the following files: Table 11-1 HPM Upgrade Package Filename Description 9806822J10P_atca-747x-ipmc-all.hpm HPM-compatible upgrade image of the IPMC firmware and the Boot Loader ATCA-7475 Installation and Use (6806800S38D)
  • Page 274 HPM-compatible upgrade image of the IPMC firmware atca-747x-bios-2.1.6.hpm HPM file contains the version 2.1.6 BIOS image atca747x_rev08.bin.hpm HPM file contains the version 0.08 FPGA image Ipmitool-1.8.9-pps-7.tgz PPS modified Ipmitool necessary for HPM upgrades on ATCA747x ATCA-7475 Installation and Use (6806800S38D)

  • Page 275: Replacing The Battery

    Appendix A Replacing the Battery Replacing the Battery Some blade variants contain an on-board battery. Its location is shown in the following figure. A battery-less variant based on SUPERCAP is available on demand. ATCA-7475 Installation and Use (6806800S38D)

  • Page 276: Figure A-1 Location Of On-Board Battery

    Replacing the Battery Figure A-1 Location of On-board Battery ATCA-7475 Installation and Use (6806800S38D)
  • Page 277 The battery provides data retention of seven years summing up all periods of actual data use. Artesyn Embedded Technologies therefore assumes that there is usually no need to replace the battery except, for example, in case of long-term spare part handling.
  • Page 278 Removing the battery with a screw driver may damage the PCB or the battery holder. To prevent this damage, do not use a screw driver to remove the battery from its holder. 2. Install the new battery following the "positive" and "negative" signs. ATCA-7475 Installation and Use (6806800S38D)

  • Page 279: Related Documentation

    The publications listed below are referenced in this manual. You can obtain electronic copies of Artesyn Embedded Technologies - Embedded Computing publications by contacting your local Artesyn sales office. For released products, you can also visit our Web site for the latest copies of our product documentation.

  • Page 280: Manufacturers' Documents

    PCI-SIG PCI Local Bus Specification Revision 2.2 PCI-X Addendum to the PCI Local Bus Specification 1.0 PICMG PICMG 3.0 Revision 2.0 Advanced TCA Base Specification PICMG 3.1 Revision 1.0 Specification Ethernet/Fiber Channel for AdvancedTCA Systems ATCA-7475 Installation and Use (6806800S38D)
  • Page 282 Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc. All other product or service names are the property of their respective owners. © 2014 Artesyn Embedded Technologies, Inc.

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