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ATCA-7475
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Artesyn ATCA-7475 manual available for free PDF download: Installation And Use Manual
Artesyn ATCA-7475 Installation And Use Manual (282 pages)
Brand:
Artesyn
| Category:
Single board computers
| Size: 18 MB
Table of Contents
Table of Contents
3
About this Manual
19
Table
23
Safety Notes
25
Sicherheitshinweise
29
1 Introduction
35
Features
35
Standard Compliances
36
Table 1-1 Standard Compliances
36
Figure 1-1 Declaration of Conformity
37
Mechanical Data
38
Product Identification
39
Ordering Information
39
Figure 1-2 Serial Number Location
39
Table 1-3 Blade Variants
40
2 Hardware Preparation and Installation
43
Unpacking and Inspecting the Blade
43
Environmental and Power Requirements
43
Environmental Requirements
44
Table 2-1 Environmental Requirements
45
Figure 2-1 Location of Critical Temperature Spots (Blade Top Side)
46
Power Requirements
47
Table 2-2 Critical Temperature Limits
47
Table 2-3 Power Requirements
48
Blade Layout
50
Figure 2-2 ATCA-7475 Blade Layout
50
Switch Settings
51
Figure 2-3 Switch Location (Bottom Side of the Blade)
51
Table 2-4 Switch SW1 Settings
52
Table 2-6 Switch SW3 Settings
53
Installing the Blade Accessories
54
DIMM Memory Modules
54
MO297 SSD Module
56
Accelerator Module
58
Installing and Removing the Blade
59
Installing the Blade
59
Removing the Blade
62
3 Controls, Indicators, and Connectors
65
Face Plate
65
Leds
66
Face Plate Leds
66
Keys
67
Connectors
67
Ethernet Connector
68
Serial COM#1 P17
68
Table 3-2 RJ45 Female Serial Line Connector Pinout
68
Figure 3-2 Ethernet Interface Connectors Pinout
69
Figure 3-3 Serial Interface Connector Pinout
69
Serial Interface Connector
69
USB Connectors
70
On-Board Connectors
70
MO297 SSD Module Connector
70
Figure 3-4 USB Connector Pinout
70
Figure 3-5 Location of MO297 SSD Module Connector
71
Figure 3-6 MO297 SSD Module Connector Pinout
72
Advancedtca Backplane Connectors
73
Figure 3-7 Location of Advancedtca Connectors
73
Figure 3-8 P10 Backplane Connector Pinout
74
Figure 3-9 P20 Backplane Connector Pinout - Rows a to D
75
Figure 3-10 P20 Backplane Connector Pinout - Rows E to H
75
Figure 3-11 P23 Backplane Connector Pinout - Rows a to D
76
Figure 3-12 P23 Backplane Connector Pinout - Rows E to H
76
Figure 3-13 P30 Backplane Connector Pinout - Rows a to D
77
Figure 3-14 P30 Backplane Connector Pinout - Rows E to H
77
Figure 3-15 P31 Backplane Connector Pinout - Rows a to D
78
Figure 3-16 P31 Backplane Connector Pinout - Rows E to H
78
Figure 3-17 P32 Backplane Connector Pinout - Rows a to D
79
Figure 3-18 P32 Backplane Connector Pinout - Rows E to H
79
4 Bios
81
Introduction
81
Accessing the Blade Using the Serial Console Redirection
82
Requirements for Serial Console Redirection
82
Default Access Parameters
82
Connecting to the Blade
83
Changing Configuration Settings
83
Main Menu
84
Boot Options
85
Selecting the Boot Device
85
Supported Boot Devices
85
By Boot Menu
87
Boot Menu
87
IPMI Boot Parameter
88
Figure 4-3 IPMI Boot Parameter
88
Restoring BIOS Default Settings
89
BIOS Setup Configuration
90
Main
90
Table 4-2 Main -> Boot Configuration
90
Advanced
91
Table 4-3 Advanced --> RTM Configuration
91
Table 4-4 Advanced --> CPU Configuration
92
Table 4-5 Advanced --> CPU Configuration -> Processor Power Management
92
Table 4-6 Advanced --> CPU Configuration -> System Agent (SA) Configuration
93
Table 4-7 Advanced --> CPU Configuration -> System Agent (SA) Configuration -> Intel (R) I/O
93
Table 4-8 Advanced --> Memory Configuration
93
Table 4-10 Advanced --> SATA Configuration
95
Table 4-11 Advanced --> Super IO Configuration
95
Table 4-9 Advanced --> USB Configuration
95
Ipmi
96
Table 4-12 Advanced --> SMBIOS Event Log
96
Security
97
Boot
98
CPU Performance Settings
98
Exit
98
Table 4-16 CPU Performance Settings
98
Independent Channel Mode
99
Memory Configuration
99
Mirrored Channel Mode
99
Lockstep Channel Mode
100
Restoring BIOS Default Settings
100
IPMI Support
101
Watchdog Support
101
BIOS Error Logging
102
Runtime Error Logging
102
Table 4-17 Logged Error Events
102
IPMI Error Logging
104
Table 4-18 BIOS Supported IPMI Events
104
SMBIOS Error Logging
106
Single-Bit ECC Memory Error
107
Table 4-19 Single-Bit ECC Memory Error Event Format
107
Table 4-20 Memory Information Definition
107
Multi-Bit ECC Memory Error
108
POST Error
108
Table 4-21 Multi-Bit ECC Memory Error Event Format
108
Table 4-22 Memory Information Definition
108
Table 4-23 POST Error Event Format
109
Table 4-24 Result First DWORD Supported POST Errors
109
Table 4-25 Result Second DWORD Supported POST Errors
109
PCI Parity Error
110
Table 4-26 PCI Parity Error Event Format
110
PCI System Error
111
Table 4-27 PCI Information Definition
111
Table 4-28 Multi-Bit ECC Memory Error Event Format
111
Table 4-29 Memory Information Definition
111
Correctable Memory Log Disabled
112
CPU Failure
112
Table 4-30 CPU Failure Event Format
112
Table 4-31 Correctable Memory Log Disabled Event Format
112
Table 4-32 Memory Information Definition
112
Log Area Reset/Cleared
113
System Boot
113
LED Usage
113
Upgrading the BIOS
113
Table 4-33 Log Area Reset/Cleared Event Format
113
Table 4-34 System Boot Event Format
113
BIOS Status Codes
114
5 Functional Description
121
Block Diagram
121
Figure 5-1 Block Diagram ATCA-7475
121
Processor
122
Memory
122
Platform Controller Hub (PCH)
123
PCH I/O Controller Features
124
PCH Intel Quickassist and Quad MAC Pcie Endpoint
125
Firmware Flashes
126
Figure 5-2 Intel Cavecreek PCH on ATCA-7475 Block Diagram
126
Ethernet Ports
127
ATCA Base if Link Status Pass through
127
Table 5-1 Ethernet Controller Types
127
Figure 5-3 FPGA to Marvel 88E6161 Base-Interface Connection
128
Marvel Switch Initialization
128
Storage Controller
129
MO297 Slimsata Embedded Solid State Disc (SSD)
129
Bios
129
Ipmc
129
Serial Redirection
130
Serial over LAN
131
Control Logic
131
Front Board Face Plate
131
Faceplate Serial Interfaces
132
Table 5-2 Faceplate Serial Interfaces
132
IPMC Debug Console
133
USB 2.0 Interfaces
133
LPC Interface
133
Trusted Platform Module
133
Table 5-3 IPMC Debug Console Destination Selection
133
Real Time Clock
134
ATCA-7470 Accelerator Module Slot
134
Smbus
135
Table 5-4 Variants of the Intel DH8900CC PCH Device
135
Table 5-6 Smbus Address Map
136
Figure 5-4 Smbus Architecture
136
6 Maps and Registers
139
Interrupt Structure
139
Figure 6-1 Interrupt Structure on ATCA-7475
139
Intel DH8900CC PCH NON-APIC (PIC Mode) D31:F0 Interrupt Mapping
140
Table 6-1 Non-APIC (PIC Mode / 8259 Mode) Interrupt Mapping
140
Intel Cavecreek PCH DH8900CC APIC (D31:F0) Interrupt Mapping
141
Table 6-2 APIC Mode Interrupt Mapping
141
NMI Generation
142
FPGA Registers
143
Registers
144
Figure 6-2 Glue Logic FPGA Block Diagram
144
Register Decoding
145
LPC Decoding
145
Table 6-5 Register Access Type
145
SPI Register Decoding
146
POST Code Register
146
Table 6-6 LPC I/O Register Map Overview
146
Table 6-8 POST Code Register
147
FPGA Register Mapping
148
LPC I/O Register Map
148
IPMC SPI Register Map
148
Table
148
Table 6-9 FPGA Register Map Overview
148
Table
150
Module Identification Register
151
Version Register
151
Serial Redirection Control Register
151
Table 6-10 Module Identification Register
151
Serial over LAN (SOL) Control Register
152
Table 6-12 Serial Redirection Control Register
152
Table 6-13 Serial over LAN Control Register
152
Serial Line Routing Register
153
RTM SPI Interface Registers
153
Table 6-14 Serial Line Routing Register
153
Table 6-15 RTM SPI Address/Command Register
154
Table 6-16 RTM SPI Write Register
154
Table 6-17 RTM SPI Read Register
154
DIMM ADR Status Register
155
Reset Registers
155
BIOS Reset Source Register
155
Table 6-18 DIMM ADR Status Register
155
Reset Mask Register
156
Table 6-19 BIOS Reset Source Register
156
BIOS IPMC Watchdog Timeout Register
157
Table 6-21 BIOS IPMC Watchdog Timeout Register
157
BIOS Push Button Enable Register
158
OS Reset Source Register
158
Table 6-22 BIOS Push Button Enable Register
158
OS IPMC Watchdog Timeout Register
159
Table 6-23 Reset Source Register
159
IPMC Watchdog Timeout Register
160
Table 6-24 os IPMC Watchdog Timeout Register
160
Table 6-25 IPMC Watchdog Timeout Register
160
IPMC Reset Source Register
161
Table 6-26 IPMC Reset Source Register
161
DIMM ADR Configuration Register
162
Table 6-27 DIMM ADR Feature Configuration Register
162
10Software Reset Register
163
11FWH_PLTRST_ Enable Register
163
Interrupt Control and Status Registers
163
Table 6-28 Software Reset Control Register
163
Table 6-29 FWH_PLTRST_ Reset Enable Register
163
External Interrupt Status Register
164
RTM Interrupt Status Register
164
Table 6-30 External Interrupt Status Register
164
Processor Hot Status Register
165
Table 6-31 Processor Hot Status Register
165
Table 6-32 Telecom Interrupt Control/Status Register
165
Telecom Interrupt Control/Status Register
165
Interrupt Mask and Map Registers
166
Table 6-33 Address Map of Interrupt Mask and Map Registers
166
Table
168
Table 6-34 Interrupt Mask and Map Registers
168
Base Interface Link Interrupt Status Register
169
PCI Express Hot Plug I2C IO Expander Registers
169
Table 6-35 Base Link Interrupt Status Register
169
Hot-Plug Virtual Pin Port Registers
170
Table 6-36 Hot-Plug Virtual Pin Port Register
170
PCA9555 Internal Register Access
172
Table 6-37 Address Control for PCA9555 Internal Register
172
Table 6-38 Content of PCA9555 Internal Register
172
Flash Status and Protection Registers
173
Table 6-39 Flash Status Register
173
Table 6-40 Default Boot SPI Flash Write Enable
174
Table 6-41 Recovery Boot SPI Flash Write Enable
174
BIOS Boot Mode Register
175
Update Channel Equalization Control Register
175
Table 6-42 BIOS Boot Mode Register
175
Table 6-43 Update Channel Equalization Control Register
175
IPMC E-Keying Status Register
176
Table 6-44 IPMC E-Keying Status Register
176
IPMC E-Keying Control Register
177
LED Status and Control Register
177
Table 6-45 IPMC E-Keying Control Register
177
Table 6-46 LED Status and Control Register
177
CPLD Revision Register
178
Spare Signals Status Registers
178
Table 6-47 CPLD Version and Spare Signal Status Register
178
Table 6-48 Spare Signal Status Register
178
DIMM Event Register
179
Table 6-49 DIMM Event Register
179
CPU Type and Presence Detection Register
180
Memory Temperature Status Register
180
Table 6-50 CPU Type and Presence Detection Register
180
Table 6-51 Memory Temperature Status Register
180
Base Interface Link Status Signals Register
181
Table 6-52 Base Interface Link Status Signals Register
181
Miscellaneous Status/Control Registers
182
Table 6-53 Misc (Ethernet Link and CPU Error) Status Register
182
Telecom Clock Control and Supervision Registers
183
Telecom Clock Device Control/Status Registers
183
Table 6-54 ACS8225B SPI Access Register
183
Table 6-55 ACS8225B SPI Status Register
183
Table 6-56 ACS8225B SPI Access Data Register
184
Table 6-57 ACS8225B Status/Control Register
184
Telecom Clock Enable and Routing Register
185
Table
185
Table 6-58 Telecom Clock Enable and Routing Register
185
Table 6-59 Supervised Telecom Clocks Reference List
186
Table 6-60 Telecom Clock Monitor Control Register
186
Table 6-61 Telecom Clock Monitor Status Register
186
Telecom Clock Monitor Registers
186
Table 6-62 Telecom Clock Monitor out of Range Register
187
Table 6-63 Telecom Clock Monitor Select Register
187
Table 6-64 Telecom Clock Monitor Time Base Register
188
Table 6-65 Telecom Clock Monitor Frequency/Period Register
190
Table 6-66 Telecom Clock Monitor Lower Limit Register
190
Table 6-67 Telecom Clock Monitor Upper Limit Register
190
Serial Management Interface (MII) Control Registers
191
Table 6-68 Management Interface PHY Address Register
191
Table 6-69 MII Management Interface Control and Address Register
191
Table 6-70 MII Management Interface Lower Byte Register
192
Table 6-71 MII Management Interface Upper Byte Register
192
Scratch Registers
193
Table 6-72 IPMC BIOS Communication Register 1
193
Table 6-73 IPMC BIOS Communication Register 2
193
Table 6-74 IPMC BIOS Communication Register 3
193
Table 6-75 LPC Scratch Register
193
Table 6-76 IPMC Scratch Register
194
7 Serial over LAN
195
Overview
195
Installing the Ipmitool
195
Configuring SOL Parameters
196
Using Standard IPMI Commands
196
Using Ipmitool
197
Establishing an SOL Session
199
8 Boot Bank Selection
201
BIOS Boot Bank Selection
201
Boot Bank Sensor
201
Fail Safe Logic
201
Figure 8-1 Failsafe Mechanism
202
Glue Logic FPGA Flash Selection
204
9 Supported IPMI Commands
205
Standard IPMI Commands
205
Global IPMI Commands
205
System Interface Commands
205
Table 9-1 Supported Global IPMI Commands
205
Table 9-2 Supported System Interface Commands
205
Watchdog Commands
206
Table 9-3 Supported Watchdog Commands
206
SEL Device Commands
207
FRU Inventory Commands
207
Table 9-4 Supported SEL Device Commands
207
Table 9-5 Supported FRU Inventory Commands
207
Sensor Device Commands
208
Table 9-6 Supported Sensor Device Commands
208
Chassis Device Commands
209
System Boot Options Commands
209
Table 9-7 Supported Chassis Device Commands
209
Table 9-8 Configurable System Boot Option Parameters
209
Table 9-9 System Boot Options Parameter #96
210
Table 9-10 System Boot Options Parameter #97
211
Table 9-11 System Boot Options Parameter #98
212
Figure 9-1 System Boot Options Parameter #100 - Information Flow Overview
213
Table 9-12 System Boot Options - Parameter #100 - Data Format
213
Table 9-13 System Boot Options Parameter #100 - SET Command Usage
214
Table 9-14 System Boot Options Parameter #100 - GET Command Usage
215
Table 9-15 System Boot Options Parameter #100 - Supported Parameters
216
Table
217
Table
218
Table 9-16 Boot_Order Devices
219
LAN Device Commands
220
Table 9-17 Supported LAN Device Commands
220
PICMG 3.0 Commands
221
Table 9-18 Supported PICMG 3.0 Commands
221
Set/Get Power Level
222
Artesyn Embedded Technologies Specific Commands
223
Serial Output Commands
223
Set Serial Output Command
223
Table 9-19 Serial Output Commands
223
Table 9-20 Request Data of Set Serial Output Command
224
Table 9-21 Response Data of Set Serial Output Command
224
Get Serial Output Command
225
Table 9-22 Request Data of Get Serial Output Command
225
OEM Command to Configure IPMI Features
226
Table 9-23 Response Data of Get Serial Output Command
226
Table 9-24 Feature Configuration Command
226
Set Feature Configuration
227
Table 9-25 Set Feature Configuration Command
227
Get Feature Configuration
228
Table 9-26 Feature Selector Assignments
228
Table 9-27 Get Feature Configuration Command
228
Pigeon Point Specific Commands
229
Table 9-28 Pigeon Point Extension Commands
229
Get Status Command
231
Table 9-30 Get Status Command Description
231
Get Serial Interface Properties Command
234
Table 9-31 Get Serial Interface Properties Command Description
234
Set Serial Interface Properties Command
235
Table 9-32 Set Serial Interface Properties Command Description
235
Get Debug Level Command
236
Table 9-33 Get Debug Level Command Description
236
Set Debug Level Command
237
Table 9-34 Set Debug Level Command Description
237
Get Hardware Address Command
238
Set Hardware Address Command
238
Table 9-35 Get Hardware Address Command Description
238
Table 9-36 Set Hardware Address Command Description
238
Get Handle Switch Command
239
Table 9-37 Get Handle Switch Command Description
239
Get Payload Communication Time-Out Command
240
Set Handle Switch Command
240
Table 9-38 Set Handle Switch Command Description
240
Table 9-39 Get Payload Communication Time-Out Command Description
240
Set Payload Communication Time-Out Command
241
Table 9-40 Set Payload Communication Time-Out Command Description
241
Disable Payload Control Command
242
Enable Payload Control Command
242
Table 9-41 Enable Payload Control Command Description
242
Table 9-42 Disable Payload Control Command Description
242
Hang IPMC Command
243
Reset IPMC Command
243
Table 9-43 Reset IPMC Command Description
243
Table 9-44 Hang IPMC Command Description
243
Graceful Reset Command
244
Table 9-45 Graceful Reset Command Description
244
Get Payload Shutdown Time-Out Command
245
Table 9-46 Get Payload Shutdown Time-Out Command Description
245
Get Module State Command
246
Set Payload Shutdown Time-Out Command
246
Table 9-47 Set Payload Shutdown Time-Out Command Description
246
Table 9-48 Get Module State Command Description
246
Disable Module Site Command
248
Enable Module Site Command
248
Table 9-49 Enable Module Site Command Description
248
Table 9-50 Disable Module Site Command Description
248
Reset Carrier SDR Repository Command
249
Table 9-51 Reset Carrier SDR Repository Command Description
249
10 FRU Information and Sensor Data Records
251
FRU Information
251
Table 10-1 FRU Information
251
MAC Address FRU OEM Records
252
Table 10-2 Artesyn ECC MAC Address Record
252
Table 10-3 Artesynecc MAC Address Descriptor
252
Table 10-4 Interface Type Assignments
253
Power Configuration
254
Sensor Data Records
254
Table 10-5 Power Configuration
254
Table 10-6 IPMI Sensors Overview
254
Figure 10-1 Location of Temperature Sensors
259
Table 10-7 Sensor Data Records
260
11 Firmware Upgrade
269
HPM.1 Firmware Upgrade
269
Overview
269
Installing the Ipmitool
269
Update Procedure
269
Interface
270
Ipmb-0
270
IPMI over LAN (BASE)
270
KCS Interface
270
IPMC Upgrade
271
BIOS/FPGA Upgrade
272
Upgrade Package
273
Table 11-1 HPM Upgrade Package
273
Replacing the Battery
275
Figure A-1 Location of On-Board Battery
276
Related Documentation
279
Artesyn Embedded Technologies - Embedded Computing Documentation
279
Table B-1 Artesyn Embedded Technologies - Embedded Computing Publications
279
Manufacturers' Documents
280
Related Specifications
280
Table B-2 Manufacturer's Documents
280
Table B-3 Related Specifications
280
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