General - Motorola R-2001A Service Manual

18-1. General. Input buffers and output latches for front panel control and display interface to the
processor are contained on the Front Panel Interface Module. Buffering and ranging circuits for the external
scope vertical, SINAD, DVM, Frequency Counter, and external scope horizontal inputs is also contained on
this module. A block diagram of the Front Panel Interface Module is shown in figure 18-1 with its schematic
shown in figure 18-2.
18-2. Input Coupling and Ranging. Scope inputs to the Range Attenuator are from the front panel jack (EXT
IN) or from the internal modulation sources (INT SCOPE TO RNG SW). An INT/EXT relay selects the input
path. The external path may be AC or DC coupled and is also the path for external DVM, Frequency Counter,
and SINAD inputs.
18-3. Four decades of attenuation from 1.0 to 0.001 are provided by the Range Attenuator. The input
impedance of the attenuator is 1.0 megohm compensated for a bandwidth of 1 MHz. A unity gain buffer amp
following the attenuator provides the drive for the DVM, Frequency Counter, and Scope Vertical Preamp
circuits.
18-4. DVM Buffer. For DC measurements the DVM Buffer provides a 2-pole low pass filter with a minimum
of 30 dB attenuation at 50 Hz. For AC measurements the bandwidth of the buffer is switched so that the
attenuation at 10 kHz is less than 0.5 dB.
18-5. Frequency Counter Preamp. The Frequency Counter Preamp has sufficient gain for 30 mV rms
sensitivity and provides hystersis for noise immunity.
18-6. Scope Vertical Preamp. A calibrated gain of 50 or a variable gain from 5 to 50 is provided by the
Vertical Preamp. The gain is control led from the front panel. For vertical scope positioning the DC bias point of
the preamp is controlled by the front panel position control. Deflection sensitivity at the VERT FROM RNG SW
output is 0.5 volt per division.
18-7. Scope Horizontal Preamp. A fixed gain of 5 in the Horizontal Preamp gives a horizontal input
sensitivity of 0.1 volt per division. Horizontal vernier gain is implemented on the front panel, and horizontal
positioning on the Scope Amplifier module. Deflection sensitivity at the HORIZ TO SCOPE AMPL is 0.5 volt
per division.
18-8. Control and Display Interface. Front panel control information is input to the processor in 4-bit
groups through the AF control bus. Priority encoders convert the multiposition switches, scope horizontal,
frequency scan, and RF step attenuator, to 4-bit codes. The processor sequentially addresses (AF ADRS BUS
0-3) each input buffer through the Address Decoder. Data in the selected buffer is then transfered to the
processor on the AF DATA BUS 0-3 lines while the AF BUS EN 2 signal is low.
18-9. A three or four bit code for each LED display group is transfered from the processor to the display latch.
The latched data is decoded and the indicated LED driver is enabled.
18-10. Two additional latches provide the processor control interface for the Range Attenuator, input
switching, and DVM Buffer control.
SECTION 18
FRONT PANEL INTERFACE MODULE (A12)
18-1