Motorola R-2001A Service Manual page 149

13-9. The Counter Control circuitry responds to a START pulse from the processor to gate the output of the
Select Switch to the Accumulator for a time period determined by the Gate Time Generator. When the gate
time has ended, or if the accumulator overflows, the Counter Control signals the processor on the END line
that the count is complete. The processor in turn disables the A/D output drivers, switches the DVM/CNTR
Buffer to the counter mode, and inputs the 16-bit accumulator information.
13-10. Gate times from 0.001 sec to 10 sec are generated by the Gate Time Generator. The SYNTH 1 kHz
signal is the reference input for the generator. Selection of the gate time is by processor control to give a five
digit or 0.1 Hz resolution frequency display.
13-11. Zero Beat. A zero beat with the incoming carrier is obtained by successively mixing the 455 kHz
IF/BFO FREQ with 500 kHz, 50 kHz, and 5 kHz. The beat signal that results from the mixing drives the ground
return circuit for the signal presence indicator.
13-12. Module Control. Control of this module is from the processor on the AF control bus. A four bit
address (AF ADRS BUS 0-3) is decoded by the Address Decode circuitry to determine which Control Latch the
control data is to be stored. The four data bits (AF DATA BUS 0-3) are then stored into the selected Control-
Latch by a pulse on the AF BUS EN 2 signal line.
13-2