System Control Bus Interface - Motorola R-2001A Service Manual

13-1. General. Frequency Counter and DVM functions with their processor interface as well as the
processor interface for the two system control buses are contained on this module. Additionally, circuitry to
complete the 10.245 MHz phase locked loop, and to zero beat the incoming carrier are also on this board. A
block diagram of the processor I/O module is shown in figure 13-1 with its schematic shown in figure 13-2.
13-2. 10.245 MHz Phase Locked Loop.
contained on this module. The 10.245 MHzVCO and the loop filter are on the received module. A sample of the
10.245 MHz second local oscillator is mixed with the SYNTH 10 MHz signal. A divide by fourty nine following
the mixer divides the 245 kHz signal from the mixer to 5 kHz. A phase comparison between the 5 kHz from the
divider and the SYNTH 5 kHz signal results in the 10.245 MHz VCO TV signal. The VCO TV signal is an error
signal which is filtered by the loop filter on the receiver to correct the VCO frequency and maintain phase lock.
13-3.

System Control Bus Interface.

Peripheral Interface Adapters (PIA). The PIA is a sing Ie integrated circuit that provides 18 input/output latches
which may either be read from or written into by the processor. Two additional inputs on the PIA provide for
processor interrupt capability. The two system control buses utilize a single PIA.
13-4. Each system control bus consists of eight lines split into four data lines and four address lines. The
address lines define the particular latch into which the data is to be stored, or the buffer from which data is to be
obtained. One additional address line, the bus enable line, is required to enable the address decoding circuitry.
Thus each control bus can have as many latches at one address as there are bus enable lines. The system
utilizes one RF bus enable and two AF bus enables for a total control bus capability of 192 bits. The second bus
enable for the AF control bus is on the processor card.
13-5. For internal timing ontonesequences.theprocessorisinterruptedevery10msec.When interrupted by
the timing input the processor stops it current process, acknowledges the interrupt, increments its time
counter and then combines as normal. The timing interrupt is the SYNTH 100 Hz input to the Bus PIA.
13-6. DVM. Inputs on the DVM to A/D signal line are digitized into a 10-bit digital word plus a sign bit and
then input to the processor through the DVM PIA. An Absolute Value circuit converts the ±1 volt bipolar input
signal to a 0-1 volt unipolar positive level with a separate digital output to indicate the sign of the input. An
Analog to Digital Converter (A/D) converts the unipolar input into a 10-bit word under processor command. A
pulse on the START line from the processor starts the A/D. When conversion is complete the A/D signals the
processor on the END line. The processor in turn enables the output drivers on the A/D, sets the DVM/CNTR
Buffer to the DVM mode, and inputs the 10bit word plus the signal bit.
13-7. For AC measurements a filter is switched on in the Absolute Value circuit so that its output is a DC level
proportional to the average value of the input sinewave. Conversion to RMS is made in the processor by
multiplying the average level by 1.11 to obtain the RMS level.
13-8. Frequency Counter.
frequency determination. For external inputs the EXT FREQ CTR line from the Front Panel Interface module
provides the input. Determination of the duplex frequency is accomplished by measuring the frequency of the
offset oscillator on the OFFSET FREQ line. Monitor frequency error is determined from the IF/BFO FREQ line
by comparing that frequency to 455 kHz. The desired signal is selected to the counter control by the Select
Switch under processor control.
SECTION 13
PROCESSOR I/O MODULE (A7)
Only part of the circuitry for the second local oscillator loop is
Interface between the processor buses and the system is through
Three possible signal sources are available to the frequency counter for
13-1