Motorola R-2001A Service Manual page 208

22-7. IEEE-488 BUS STRUCTURE
22-8. The following discussion briefly describes the 488 Bus operation. It is not a complete definition of the
total bus structure or capability. For complete information a copy of IEEE Standard 488 should be obtained.
22-9. Bus Signals. The IEEE-488 Bus consists of 16 parallel lines. The lines are divided into three groups.
Lines DI01-DI08, Data Input Output, form the 8-bit data bus for the bidirectional transfer of control and ASC II
characters. Three handshake lines, Data Valid (DAV), Not Ready for Data (NRFD), and Not Data Accepted
(NDAC), control the transfer of data on the data bus. The remaining five lines can be termed the bus
management lines with functions as follows:
Attention (ATN)
Interface Clear (IFC)
Service Request (SRQ)
Remote Enable (REN)
End or Indentify (EOI)
22-10. Data Transfer. Each byte of data that is transferred across the data bus is synchronized with a
handshaking procedure. This procedure allows devices with different data transfer rates to share the same
bus. The handshake cycle starts when thesourcedevicewhichhasdatatotransferchecksforafalsecondition
on the NRFD line. When NRFD is false, all devices on the bus are ready to accept data. The source then puts the
data onto the data bus and sets the DAV to its true state. The acceptor devices input the data, set the NRFD line
to its true state, and when ready sets the NDAC line to its false state. Because the NRFD and NDAC lines are
wire-ORed the line will not go to the false state until all devices on the bus have released the line. Thus the
slowest device on the bus determines the transfer rate. When the NDAC line goes false the source devices sets
the DAV false which in turn causes the acceptor devices to set the NDAC line true. When the acceptor devices
have completed processing the data byte just received they allow the NRFD line to go to the false state
completing the handshake. As the data transfer continues the cycle repeats for each data byte.
22-11. Bus Address. Each device on the bus is assigned a four bit address by the programer. The address
assigned to the device is set by an address switch within the device. On the analyzer the address switch is on
the IEEE Interface Module. Only the top four switches are used to set the address. The fifth switch is unused.
To set the address use the binary equivalent of the address number and set the switches to the ON position for
a logic 1. The least significant bit is the top switch.
22-12. Programing
22-13. Programing the system analyzer consists of first addressing the unit as a listener, transferring the
control commands to the unit, and then sending a command termination sequence. To obtain data from the
system, the pertinent control commands are first transferred to the unit and then the unit is addressed as a
talker. As a talker the system outputs onto the bus the data requested by the control commands.
22-14. The bus controller is the central part of the automatic system. The program, consisting of sequences
of analyzer control commands and sequences of controller instructions for handling the return data, is
contained within the controller. The user must initially write the program so that the desired test sequences
and data outputs will be obtained. The following paragraphs define the instruction set and data formats that
can be used to control or will be returned from the system analyzer. The user must insure that the controller is
compatible with the IEEE-488 Standard bus and that its program is correct for the instruments on the bus.
— When true the data bus carries an address or
a comand when false it carries data.
— When true all devices on the bus are placed
in a known quiescent state.
— Indicates a device on the bus needs service.
— Enables the remote control feature of the devices on the bus.
— Indicates the end of a multiple byte transfire.
22-3