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VX800UT
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Manuals and User Guides for VIA Technologies VX800UT. We have
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VIA Technologies VX800UT manual available for free PDF download: Programming Manual
VIA Technologies VX800UT Programming Manual (494 pages)
Brand:
VIA Technologies
| Category:
Control Unit
| Size: 6 MB
Table of Contents
Table of Contents
3
Table of Contents
4
Registers Overview
9
Register Document Introduction
9
Table 1. Vx800 / Vx820 Series Feature Comparison Table
9
Module and Register Scope Definitions
10
Module Name Abbreviations
10
Register Scope Map Within Modules
10
Register Table Format
12
Column Definitions
12
Attribute Definitions
12
Special Default Value Definitions
12
Pci Arbiter Control
13
Pci Configuration Space I/O
13
North Module Register Descriptions
14
Device 0 Function 0 (D0F0): Host Controller
14
Header Registers (00-3Fh)
14
Multiple Function and Legacy Space Access Control (4F-C6H)
17
Control Registers for Integrated Graphics / Video Processor (C7-Ffh)
18
Device 0 Function 1 (D0F1): Error Reporting
20
Header Registers (00-3Fh)
20
Host Bus Error Report (60-6Fh)
23
Device 0 Function 2 (D0F2): Host Bus Control
24
Header Registers (00-3Fh)
24
Host CPU Control (50-5Fh)
27
Table 2. Dynamic Defer Snoop Stall Table
27
Table 3. Cpu Write Request Policy
30
Table 4. Host / Dram Bandwidth Policy
31
Host Interface DRDY Timing Control (60-6Fh)
32
Host AGTL+ I/O Circuit (70-8Fh)
35
Miscellaneous Control (90-9Eh)
43
Device 0 Function 3 (D0F3): Dram Bus Control
44
Header Registers (00-3Fh)
44
Table 5. Programming Setting for Dram Channels
44
DRAM Rank (Row) Ending / Beginning Address (40-4Fh)
47
MA Map / Command Rate (50-53H)
49
Table 6. Rank Ma Map Type Table
49
Physical-To-Virtual Rank Mapping (54-57H)
50
Table 7. Dram Bank Address Table
50
Table 8. Rank Interleave Address Table
50
Virtual Rank Interleave Address Select / Enable (58-5Fh)
51
Figure 1. DIMM / Channel Mapping Diagram
52
DRAM Timing (60-64H)
53
DRAM Queue / Arbitration (65-67H)
55
DRAM Control (68-69H)
56
Refresh Control (6A-6Bh)
56
DDR SDRAM Control (6C-6Fh)
57
DRAM Signal Timing Control (70-7Fh)
59
Read-Only Control (7C-7Fh)
62
Shadow RAM Control (80-83H)
62
Table 9. Cpu-To-Smram Cycle Flow
63
DRAM above 4G Support (84-8Dh)
64
DRAM Clocking Control (90-9Fh)
66
UMA Registers (A0-Afh)
70
GMINT and AGPCINT Registers (B0-Bfh)
72
DDR2 - I/O Pad Termination and Driving Control (D0-Dfh)
74
Table 10. MD Pads Odt Control in Different Dram Mode
75
Table 11. Pad Odt Control Group Setting
75
DRAM Driving Control (E0-Ebh)
81
Table 12. Physical Pin to Driving Group Mapping Table
81
DRAM CKG Control (EC-Efh)
83
DQ / DQS CKG Output Delay Control (F0-F9H)
84
DDR2 - DQ De-Skew Control (FA-Ffh)
85
Table 13. Scmd and Ma Pins Power Saving Mode Setting
87
Table 14. Chip Select Pins Power Saving Mode Usage
87
Device 0 Function 4 (D0F4): Power Management Control
88
Header Registers (00-3Fh)
88
Power Management Control (80-Efh)
90
Device 0 Function 5 (D0F5): Apic and Central Traffic Control
99
Header Registers (00-3Fh)
99
Legacy APIC Base I/O Registers (40-5Fh)
101
Central Traffic - Downstream Control (60-7Fh)
103
Central Traffic - Upstream Control (80-85H)
105
Pcie Message Controller and Power Management (A0-Ffh)
107
Device 0 Function 6 (D0F6): Scratch Registers
110
Header Registers (00-3Fh)
110
Scratch Registers (40-7F)
112
Hash Data Control Registers (C0-Ffh)
113
Device 0 Function 7 (D0F7): North-South Module Interface Control
116
Header Registers (00-3Fh)
116
North-South Module Interface Control (40-60H)
119
Shadow RAM Control (61-6Fh)
119
Host-PCI Bridge Control (70-Ffh)
121
Device 2 Function 0 (D2F0) - PCI Express Root Port G0 (PCI-To-PCI Virtual Bridge)
122
Table 15. Pcie Port Support
122
Header Registers (00-3Fh)
123
PCI Express Capability Registers (40-67H)
130
PCI Power Management Capability Structure Registers (68-6Fh)
136
PCI Message Signal Interrupt (MSI) Capability Structure Registers (70-87H)
137
Message Signal Interrupt (MSI) Capability Registers (88-97H)
138
Subsystem ID and Subsystem Vendor ID Capability Registers (98-9Fh)
138
PCI Express Transaction Layer Registers (A0-Afh)
139
PCI Express Data Link Layer Registers (B0-Bfh)
143
PCI Express Physical Layer Registers (C0-Cfh)
148
Figure 2. Loop Back Mode Selections
148
Device 2 Function 0 (D2F0) - Pci Express Root Port G0 Extended Space
157
Advanced Error Reporting Capability (100-13Fh)
157
Virtual Channel Capability (140-14Fh)
160
VC0 Resource (150-15Bh)
161
VC1 Resource (15C-19Fh)
162
Device 3 Function 0 (D3F0) - PCI Express Root Port 0 (PCI-To-PCI Virtual Bridge)
163
Header Registers (00-3Fh)
163
PCI Express Capability Registers (40-67H)
170
PCI Power Management Capability Structure Registers (68-6Fh)
176
PCI Message Signal Interrupt (MSI) Capability Structure Registers (70-87H)
177
Message Signal Interrupt (MSI) Capability Registers (88-97H)
178
Subsystem ID and Subsystem Vendor ID Capability Registers (98-9Fh)
178
PCI Express Transaction Layer Registers (A0-Afh)
179
PCI Express Data Link Layer Registers (B0-Bfh)
183
Figure 3. Loop Back Mode Selections
188
PCI Express Physical Layer Registers (C0-Cfh)
188
Table 18. Mapping Table for D3F1 Rxc3
228
PCI Express Power Management Module Registers (D0-D3H)
230
PCI Express Message Controller Related Registers (D8-Dfh)
231
PCI Express Electrical PHY Registers (E0-Efh)
232
PCI Express Electrical PHY Test Registers (F0-Ffh)
233
Table 17. Mapping Table for D3F0 Rxc3
190
PCI Express Power Management Module Registers (D0-D3H)
192
PCI Express Electrical PHY Registers (E0-Efh)
193
PCI Express Message Controller Related Registers (D8-Dfh)
193
PCI Express Electrical PHY Test Registers (F0-Ffh)
194
Device 3 Function 0 (D3F0) - Pci Express Root Port 0 Extended Space
196
Advanced Error Reporting Capability (100-13Fh)
196
Virtual Channel Capability (140-14Fh)
199
VC0 Resource (150-15Bh)
200
VC1 Resource (15C-19Fh)
201
Device 3 Function 1 (D3F1) - PCI Express Root Port 1 (PCI-To-PCI Virtual Bridge)
202
Header Registers (00-3Fh)
202
PCI Express Capability Registers (40-67H)
209
PCI Power Management Capability Structure Registers (68-6Fh)
215
PCI Message Signal Interrupt (MSI) Capability Structure Registers (70-87H)
216
Message Signal Interrupt (MSI) Capability Registers (88-97H)
217
Subsystem ID and Subsystem Vendor ID Capability Registers (98-9Fh)
217
PCI Express Transaction Layer Registers (A0-Afh)
218
PCI Express Data Link Layer Registers (B0-Bfh)
222
PCI Express Physical Layer Registers (C0-Cfh)
226
Figure 4. Loop Back Mode Selections
226
Device 3 Function 1 (D3F1) - Pci Express Root Port 1 Extended Space
235
Advanced Error Reporting Capability (100-13Fh)
235
Virtual Channel Capability (140-14Fh)
238
VC0 Resource (150-15Bh)
239
VC1 Resource (15C-19Fh)
240
Pci Express Root Complex Register Block - Host
241
Virtual Channel Capability (000-00Fh)
241
VC0 Resource (010-01Bh)
242
Root Complex Link Declaration Enhanced Capability (040-04Fh)
243
Link Entry for PEG0 (050-05Fh)
243
Link Entry for PE0 (060-06Fh)
244
Link Entry for PE1 (070-07Fh)
244
Link Entry for HDAC (080-08Fh)
245
VC Arbitration Timer (200-20Fh)
246
Port Arbitration Timer for VC0 (210-219H)
246
Host Side Upstream Arbitration Timers (230-23Fh)
248
PXPTRF (Central Traffic Controller) P2P Arbitration Timer of Pcie (250-253H)
250
Table 16. Mapping Table for D2F0 Rxc3
150
PCI Express Power Management Module Registers (D0-D3H)
152
PCI Express Electrical PHY Registers (E0-Efh)
153
PCI Express Message Controller Related Registers (D8-Dfh)
153
PCI Express Electrical PHY Test Registers (F0-Ffh)
155
South Module Register Descriptions
251
Legacy I/O Ports
251
Keyboard Controller I/O Registers
253
Table 19. Keyboard Controller Command Codes
255
DMA Controller I/O Registers
257
DMA Controller Shadow Registers
258
Interrupt Controller I/O Registers
259
Interrupt Controller I/O Shadow Registers
259
Timer / Counter I/O Registers
260
Timer / Counter Shadow Registers
260
CMOS / RTC I/O Registers
260
Table 20. Cmos Register Summary
261
Keyboard / Mouse Wakeup Index / Data Registers
263
Keyboard / Mouse Wakeup Registers
264
Memory Mapped I/O Apic Registers
266
Indexed I/O APIC Registers
267
Table 21. I/O Redirection Table
268
Indexed I/O Uart Dma Control Registers
270
Device 12 Function 0 (D12F0) - Sdio Host Controller
272
PCI Configuration Space Header (00-3Fh)
272
PCI Device Specific Registers (40-Ffh)
274
SDIO Host Standard Registers (00-Ffh)
279
Table 22. Determination of Transfer Type
280
Irda Host Controller I/O Space Registers
288
Table 23. Programming Values for I/O Registers at Offset 16-19H
290
Device 13 Function 0 (D13F0) - Secure Digital Memory Card Controller
299
PCI Configuration Space Header (00-3Fh)
299
PCI Card Reader - Specific Configuration Registers (40-Ffh)
303
SDC MMIO Registers (00-Ffh)
305
Table 24. Command Type Field Encodings
306
Data DMA Control Registers (00-Ffh)
313
CICH DMA Control Registers (00-Ffh)
315
PCI Control Registers (00-Ffh)
318
Device 15 Function 0 (D15F0): Serial Ata & Eide Controller
320
Header Registers (00-3Fh)
320
Table 25. Ide/Sata Support Option
320
SATA Registers (40-47H)
326
EIDE Registers (48-54H)
328
SATA Link Control Registers (55-56H)
330
SATA PHY Control Registers (57-5Eh)
331
SATA Hot Plug and RAMBIST Status Registers (5F-63H)
333
SATA Analog PHY Control (64-77H)
334
Miscellaneous Registers (78-7Fh)
339
SATA Transport Control Registers (80-8Fh)
340
SATA SCR Registers (A0-Afh)
342
Legacy / Back Door Registers (B0-Bfh)
344
EIDE Registers (C0-Ffh)
346
Device 16 Function 0-2 (D16F0-F2) - Usb 1.1 Uhci Ports 0-5
350
PCI Configuration Space Header (00-3Fh)
350
USB 1.1-Specific Configuration Registers (40-Ffh)
353
USB 1.1 I/O Registers (00-13H)
357
Device 16 Function 4 Registers - Usb 2.0 Ehci
358
PCI Configuration Space Header (00-3Fh)
358
USB 2.0-Specific Configuration Registers (40-Fch)
361
EHCI USB 2.0 I/O Registers (00-B3H)
368
Device 17 Function 0 (D17F0) - Bus Control and Power Management
372
PCI Configuration Space Header (00-3Fh)
372
ISA Bus Control (40-49H)
374
LPC Firmware Memory Control (4A-4Bh)
378
Miscellaneous Control (4C-4Fh)
378
Function Control (50-51H)
380
Serial IRQ, LPC and PC / PCI DMA Control (52-53H)
381
Plug and Play Control - PCI (54-57H)
382
Table 26. Pnp Irq Routing Table
383
Table 27. Internal Apic, Pci Devices Irq Routing Table
383
Table 28. Hpet Irq Routing Table
383
GPIO and Miscellaneous Control (58-5Bh)
384
Programmable Chip Select (PCS) Control (5C-66H)
386
Output Control (67H)
387
High Precision Event Timers (HPET) (68-6Bh)
388
ISA Decoding Control (6C-6Fh)
389
PCI I/O Cycle Control (74-7Fh)
391
Power Management-Specific Configuration Registers (80-Cfh)
394
UART / FIR Misc Control Registers (B0-Bfh)
406
System Management Bus-Specific Configuration Registers (D0-E7H)
409
Table 29. C3 Latency Configuration Table
412
Table 30. C4 Latency Configuration Table
413
Watchdog Timer Registers (E8-Ffh)
416
ACPI IO Space Registers (PMIO 00-0Bh)
417
Processor Power Management Registers (PMIO 10-16H)
420
General Purpose Power Management Registers (PMIO 20-52H)
421
IO Trap Registers (PMIO 54-69H)
433
Watchdog Timer Memory Base (PM-MMIO 00-07H)
438
System Management Bus I/O Space Registers (SMIO 00-0Fh)
439
Spi Controller
445
Device 17 Function 7 (D17F7): South-North Module Interface Control
451
PCI Configuration Space Header (00-3Fh)
451
South -North Module Interface Control (40-5F)
453
DRAM Configuration (60H)
456
Shadow RAM Control (61-64H)
457
Conventional PCI Bus Control (70-7Fh)
458
HDAC Control (D0-Dfh)
462
Dynamic Clock Control (E0-E3H)
462
DRAM above 4G Support (E4-Ffh)
464
Device 19 Function 0 (D19F0): Pci to Pci Bridge
465
PCI Configuration Space Header (00-3Fh)
465
Device 20 Function 0 (D20F0) - High Definition Audio Controller (Hdac)
471
PCI Configuration Space Header (00-3Fh)
471
HDAC PCI Extended Configuration Space (40-260H)
474
High Definition Audio Controller Memory Mapped I/O Registers (Hdac-Mmio)
481
Global Capabilities and Control (00-1Bh)
481
Interrupt Control (20-27H)
483
Synchronization Control (30-3Bh)
483
HDAC CORB (Command Output Ring Buffer) Control (40-4Eh)
484
HDAC RIRB (Response Input Ring Buffer) Control (50-5Eh)
485
HDAC Immediate Command Control (60-69H)
487
DMA Position Base Address (70-77H)
488
HDAC Stream Descriptors (80-17Fh)
489
Alias Registers (2030-2167H)
494
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