VIA Technologies SOM-9X35 Design Manual
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VIA Technologies SOM-9X35 Design Manual

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DESIGN GUIDE
Carrier Board
for SOM-9X35 Module
1.00-18012022

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Summary of Contents for VIA Technologies SOM-9X35

  • Page 1 DESIGN GUIDE Carrier Board for SOM-9X35 Module 1.00-18012022...
  • Page 2 VIA Technologies, Inc. reserves the right the make changes to the products described in this manual at any time without prior notice.
  • Page 3 Carrier Board Design Guide for SOM-9X35 Module Revision History Revision Date Description 1.00 18/01/2022 Initial release...

  • Page 4: Table Of Contents

    Ground Planes Under Pads ......................10 2.2.8 Differential Pair Signals ........................ 11 2.2.9 Length Matching .......................... 11 SOM-9X35 Module & M.2 Slot Specification Overview ................15 SOM-9X35 Module Placement ......................15 SOM-9X35 Module & Carrier Board Dimensions ................16 M.2 Slot .............................. 17 3.3.1 M.2 Slot Dimensions ........................
  • Page 5 Carrier Board Design Guide for SOM-9X35 Module 4.4.2 MIPI CSI Layout & Routing Recommendations ................42 4.4.3 MIPI CSI Reference Schematics ....................45 USB Interface ............................48 4.5.1 USB Signal Definition ........................48 4.5.2 USB Layout & Routing Recommendations .................. 49 4.5.3...
  • Page 6 Carrier Board Design Guide for SOM-9X35 Module 4.17.1 Gas Gauge Signal Definition ......................69 4.17.2 Gas Gauge Design Notes ......................70...
  • Page 7 Figure 26: Preferred symmetrical breakout ......................13 Figure 27: Preferred breakout of differential pairs ....................14 Figure 28: SOM-9X35 module placement example on the carrier board ............15 Figure 29: Dimensions of the SOM-9X35 module ....................16 Figure 30: Dimensions of the reference carrier board ..................16 Figure 31: Dimensions of the M.2 slot (top view) ....................
  • Page 8 Figure 75: SOM-9X35 BATSNS reference circuitry ....................61 Figure 76: SOM-9X35 PWM level shift reference circuitry .................. 62 Figure 77: SOM-9X35 I2C level shift IC reference circuitry .................. 63 Figure 78: SOM-9X35 I2C level shift reference circuitry ..................63 Figure 79: SOM-9X35 I2C level shift IC reference circuitry .................. 64 Figure 80: SOM-9X35 MCU IC reference circuitry ....................
  • Page 9 Table 17: MIPI CSI1 signal definition ........................42 Table 18: MIPI CSI layout guidelines ........................43 Table 19: SOM-9X35 MIPI CSI0 4-lane trace & via delay ..................43 Table 20: SOM-9X35 MIPI CSI0A 2-lane trace & via delay.................. 44 Table 21: SOM-9X35 MIPI CSI0B 2-lane trace & via delay .................. 44 Table 22: SOM-9X35 MIPI CSI1 4-lane trace &...

  • Page 10: Introduction

    This document provides design guidelines and rule recommendations for the developers of a carrier board that supports the features of VIA SOM-9X35 module. This document includes the layout and routing guidelines for general board designs and major underlying interfaces (ex. MIPI, LVDS, HDMI, USB). In addition, the document includes the placement and mechanical information on the M.2 slot which is used to provide high-speed...

  • Page 11: Acronyms Used

    Carrier Board Design Guide for SOM-9X35 Module 1.2 Acronyms Used Term Description Analog to Digital Converter AMIC Analog Microphone Jack ASIC Application-specific Integrated Circuit Bus Access Manager/Module BLSP BAM Low Speed Peripheral Battery Management System CMOS Complementary Metal Oxide Semiconductor...

  • Page 12: I/O Parameter Definitions

    Carrier Board Design Guide for SOM-9X35 Module 1.3 I/O Parameter Definitions Symbol Description Pad attribute Analog Input (does not include the pad circuitry) Analog Output (does not include the pad circuitry) Bidirectional digital with CMOS input Digital Input (CMOS) Digital Output (CMOS)

  • Page 13: General Carrier Board Recommendations

    Carrier Board Design Guide for SOM-9X35 Module 2. General Carrier Board Recommendations This section contains general guidelines for the PCB stack-up and the layout of traces. The general guide lines for routing style, topology, and trace attribute recommendations are also discussed.

  • Page 14: 6-Layer Pcb Stack-Up Example

    Carrier Board Design Guide for SOM-9X35 Module 2.1.1 6-Layer PCB Stack-up Example The following figure shows the recommended 6-layer PCB stack-up design for the carrier board of the VIA SOM- 9X35 module. Solder mask = 0.4mil (Er=3.5) Pla�ng = 0.8mil LAYER 1 TOP = 0.5oz (0.8mil)

  • Page 15: General Layout & Routing Guidelines

    Carrier Board Design Guide for SOM-9X35 Module 2.2 General Layout & Routing Guidelines This section provides general layout rules and routing guidelines for designing carrier boards for the SOM-9X35 module. 2.2.1 General Layout & Routing Guidelines Topology is the physical connectivity of a net or a group of nets. There are two types of topologies for a carrier board layout: point-to-point (P2P) and multi-drop.

  • Page 16: General Trace Attribute Recommendation

    Carrier Board Design Guide for SOM-9X35 Module 2.2.2 General Trace Attribute Recommendation A 5mil trace width and 15mil spacing are generally advised for most signal traces on a carrier board layout. To reduce trace inductance, the minimum power trace width is recommended to be 30mil.

  • Page 17: General Clock Routing Considerations

    Carrier Board Design Guide for SOM-9X35 Module 2.2.3 General Clock Routing Considerations The clock routing guidelines are listed below: • The recommended clock trace width is 5mil. • The minimum space between one clock trace and adjacent clock traces is 20mil. The minimum space from one segment of a clock trace to other segments of the same clock trace is at least two times of the clock width.

  • Page 18: Trace Bend Geometry

    Carrier Board Design Guide for SOM-9X35 Module 2.2.4 Trace Bend Geometry When routing high-speed signals, bends should be minimized. If bends are needed, use 135° bends instead of 90°. Figure 13: Use 135° bends instead of 90° Serpentine traces (also called meander) are often needed when a certain trace length needs to be achieved.

  • Page 19: Trace Stubs

    Carrier Board Design Guide for SOM-9X35 Module 2.2.6 Trace Stubs Long stub traces can act as antennas and therefore increase problems complying with EMC standards. Stub traces can also produce reflections which negatively impacts signal integrity. Common sources for stubs are pull-up or pull-down resistors on high-speed signals.

  • Page 20: Differential Pair Signals

    Carrier Board Design Guide for SOM-9X35 Module 2.2.8 Differential Pair Signals It is not permitted to place any components or vias between the differential pairs, even if the signals are routed symmetrically. Components and vias between the pairs could lead to EMC compliance problems and create an impedance discontinuity.

  • Page 21: Figure 21: Route Pairs On The Same Layer, Place Same Amount Of Vias

    Figure 21: Route pairs on the same layer, place same amount of vias 2.2.9.1 SOM Module Package Breakout Length Matching As to SOM-9X35 module, high speed differential interface such as HDMI, USB ,LVDS, MIPI, and SDIO need to do package breakout length mismatching.

  • Page 22: Figure 24: Length Differences Need To Be Compensated In Each Segment

    Carrier Board Design Guide for SOM-9X35 Module Each segment of a differential pair connection needs to be matched individually. A connection can be segmented by a connector, serial coupling capacitors or vias. The two bends in the following figure would compensate each other.

  • Page 23: Figure 27: Preferred Breakout Of Differential Pairs

    Carrier Board Design Guide for SOM-9X35 Module If the space between the pads permits, try to add a small loop to the shorter trace. This is the preferred solution for matching the length difference as opposed to creating a serpentine trace.

  • Page 24: Som-9X35 Module & M.2 Slot Specification Overview

    The following figure shows the depiction of the top view of the carrier board PCB with the appropriate amount of space reserved for the SOM-9X35 module. SOM-9X35 Module 45mm 60mm Carrier Board Figure 28: SOM-9X35 module placement example on the carrier board...

  • Page 25: Som-9X35 Module & Carrier Board Dimensions

    Carrier Board Design Guide for SOM-9X35 Module 3.2 SOM-9X35 Module & Carrier Board Dimensions The following figures show the mechanical dimensions of the SOM-9X35 module and the reference carrier board (VAB-935). Figure 29: Dimensions of the SOM-9X35 module 134.2mm 67.5mm 134.2mm...

  • Page 26: Slot

    Carrier Board Design Guide for SOM-9X35 Module 3.3 M.2 Slot The M.2 slot can handle high-speed signals and comprises 132 pins to connect the SOM-9X35 module. Table 5 shows the specifications of the sample M.2 slot. M.2 Slot Description (VIA Part Number) 99H30-071127 Conn Slot 2E0BC21-S85BM-7H M.2 (NGFF) Connector (KEYM) 75PIN SMD right angle...

  • Page 27: Slot Height Notes

    SOM-9X35 module bottom heat sink and carrier board top layer components. For example, if the 0402 components (height less than 0.5mm) are placed on the carrier board top layer (under the SOM-9X35 module), then the M Key M.2 connector height should be ≥5mm.
  • Page 28 Carrier Board Design Guide for SOM-9X35 Module Power Voltage PIN# PIN Name GPIO# Assignment Function Level Domain Reset MT6390/ AVDD28_ Earphone MIC, J2.6 ACCDET MT6357 2.8V ACCDET ACCDET ACCDET MT8365 AVDD33_ J2.7 USB_DM_P0 3.3V USB_DM_P0 1st USB2.0 OTG D- USB_DM_P0...
  • Page 29 Carrier Board Design Guide for SOM-9X35 Module Power Voltage PIN# PIN Name GPIO# Assignment Function Level Domain Reset MT8365 EINT131/ MT8365 GPIO131/ DVDD18_ GPIO131,default for J2.22 EXT_GPIO2 1.8V I, PD EXT_GPIO2 O*TDM_ NFC_CARD_INT, input, TX_MCK/ high active O*I2S3_MCK MT6390/ Battery Gas Gauge J2.23...
  • Page 30 Carrier Board Design Guide for SOM-9X35 Module Power Voltage PIN# PIN Name GPIO# Assignment Function Level Domain Reset MT8365 SPI_CK,SPI Bus clock EINT27/ DVDD18_ J2.32 SPI_CK 1.8V I, PD SPI_CK output, default for GPIO27/ motor driver O*SPI_CLK MT8365 EINT115/ GPIO115/...
  • Page 31 Carrier Board Design Guide for SOM-9X35 Module Power Voltage PIN# PIN Name GPIO# Assignment Function Level Domain Reset MT8365 EINT38/ GPIO38/ O:UTXD1/ UART1 TXD output, DVDD18_ J2.40 UTXD1 I1:URXD1/ 1.8V I, PD UTXD1 default connect to O:URTS2/ RS232 transceiver O*I2S1_...
  • Page 32 Carrier Board Design Guide for SOM-9X35 Module Power Voltage PIN# PIN Name GPIO# Assignment Function Level Domain Reset LT8618SXB HDMI_ HDMI1.4 output,TX_ J2.51 TX_CH0_M 3.3V TX_CH0_M TX_D0- VCC33 MT8365 Connect to firmware EINT24/ DVDD18_ J2.52 KPCOL0 1.8V I, PU KPCOL0...
  • Page 33 Carrier Board Design Guide for SOM-9X35 Module Power Voltage PIN# PIN Name GPIO# Assignment Function Level Domain Reset MT6390/ DC input voltage J1.2 VIN_DC MT6357 3.4~4.2V VIN_DC Power VIN_DC input, Adapter or VIN_DC Battery plug in detect LT8618SXB HDMI_ J1.3 TX_DDCSCL 3.3/5V...
  • Page 34 Carrier Board Design Guide for SOM-9X35 Module Power Voltage PIN# PIN Name GPIO# Assignment Function Level Domain Reset MT8365 AVDD12_ Camera2 MIPI CSI1 J1.17 CSI1B_L0N 1.2V CSI1B_L0N CSI1B_L0N CSI0 4-lane D1- MT8365 EINT87/ DVDD28_ SDIO3.0 Bus CMD, J1.18 MSDC1_CMD GPIO87/ 3.0V...
  • Page 35 Carrier Board Design Guide for SOM-9X35 Module Power Voltage PIN# PIN Name GPIO# Assignment Function Level Domain Reset MT8365 CTP interrupt input, EINT78/ ENIT_CTP_ DVDD18_ High active, default J1.30 GPIO78/ 1.8V I, PD EINT78 connect to capacitive CMHSYNC/ touch panel...
  • Page 36 Carrier Board Design Guide for SOM-9X35 Module Power Voltage PIN# PIN Name GPIO# Assignment Function Level Domain Reset MT8365 DSI_ LCM MIPI DSI 4-lane AVDD18_ J1.50 DSI_D2N D2N/LVDS_ 1.8V DSI_D2N D2- /LVDS TX 4-lane TX_D0N MT8365 Camera1 MIPI CSI0 AVDD12_ J1.51...

  • Page 37: Slot Reference Schematics

    Carrier Board Design Guide for SOM-9X35 Module Power Voltage PIN# PIN Name GPIO# Assignment Function Level Domain Reset MT8365 EINT20/ LCM_RST,LCD Reset DVDD18_ J1.72 LCM_RST GPIO20/ 1.8V I, PD LCM_RST output, High pulse LCM_RST/ active O:PWM_B MT8365 Camera MIPI CSI0...

  • Page 38: Figure 35: M.2 Slot Reference Circuitry (Part 2)

    Carrier Board Design Guide for SOM-9X35 Module CSI0A_L2P [17] CSI0A_L2P GND14 CSI0A_L2N DISP_PWM [17] CSI0A_L2N DISP_PWM [12] GND13 3.3V_5 LCM_RST LCM_RST [11] GND12 3.3V_4 CSI0A_L1P LCM_ENP [17] CSI0A_L1P LCM_ENP [11,12] PEDET 3.3V_3 CSI0A_L1N [17] CSI0A_L1N LCM_ENN [12] N/C_19 SUSCLK Camera1...

  • Page 39: Layout & Routing Recommendation

    SOM-9X35 module. 4.1 HDMI Interface The SOM-9X35 module features one HDMI interface. The HDMI interface uses four control signals, one differential clock, and three differential data pair signals that carry video and audio signals.

  • Page 40: Hdmi Layout & Routing Recommendations

    Carrier Board Design Guide for SOM-9X35 Module 4.1.2 HDMI Layout & Routing Recommendations HDMI Signal Differen�al Pair Sig M Sig P Reference Plane Figure 38: HDMI differential trace width and spacing example HDMI Signal Single-ended Reference Plane Figure 39: HDMI single-ended trace width and spacing example...

  • Page 41: Hdmi Reference Schematics

    6.75 Inter-pair TX_CH1_M 577.373 83.37 TX_CH1_P -8.59 -1.24 29.74 Pair-to-Pair TX_CH1_M -10.72 -1.55 Table 09: SOM-9X35 HDMI trace & via delay 4.1.3 HDMI Reference Schematics HDMI Output Port HDMI_OUT_D3- TX_CLK_M HDMI_OUT_D3+ TX_CLK_P EOW S201212M900 90 OHM±25% 100MHZ 2.0mm*1.2mm*1.2mm/4PAD HDMI_OUT_D2+ HDMI_OUT_D2-...

  • Page 42: Figure 41: Hdmi Reference Circuitry (Part 2)

    HDMI DDC SCL capacitance loading ≤50pF • HDMI CEC capacitance loading ≤150pF HDMI CEC should not be pulled High on the carrier board. (It is already pulled High on the VIA SOM-9X35 module.) • High level: 2.5V≤V-CEC ≤3.6V. HDMI DDC SDA/ DDC SCL must be pulled High to 5V_HDMI on the carrier board.

  • Page 43: Mipi Dsi Interface

    Carrier Board Design Guide for SOM-9X35 Module 4.2 MIPI DSI Interface The SOM-9X35 module features a MIPI DSI interface. The MIPI DSI interface has four differential pair signals that carry video display signals. 4.2.1 MIPI DSI Signal Definition The following table provides the definition of the MIPI DSI signals that are implemented in the M.2 slot.

  • Page 44: Mipi Dsi Layout & Routing Recommendations

    Carrier Board Design Guide for SOM-9X35 Module 4.2.2 MIPI DSI Layout & Routing Recommendations DSI Signal Differen�al Pair Sig M Sig P Reference Plane Figure 44: MIPI DSI differential trace width and spacing example Metrics Information/Design Guidance General Information Data rate DSI –...

  • Page 45: Mipi Dsi Reference Schematics

    0.46 Inter-pair DSI_D3N 1525.48 252.62 DSI_D3P 17.15 23.8 0.82 Pair-to-Pair DSI_D3N -10.72 29.74 -1.55 Table 12: SOM-9X35 MIPI DSI trace & via delay 4.2.3 MIPI DSI Reference Schematics MIPI_D0_N DSI_D0A_N LCM_LEDA LCD_LEDA VDDIO_LCD DSI_D0A_N [13] BLM15PX121SN1D MIPI_D0_P DSI_D0A_P LCD_SHLR FB18...

  • Page 46: Lcd Backlight & Bias Voltage Reference Schematics

    2.2uF Figure 46: LCD backlight & bias voltage reference circuitry 4.3 LVDS Interface The SOM-9X35 module features an LVDS interface. The LVDS interface has four differential pair signals that carry video display signals. 4.3.1 LVDS Signal Definition The following table provides the definition of the LVDS signals that are implemented in the M.2 slot.

  • Page 47: Figure 47: Lvds Routing Topology

    Carrier Board Design Guide for SOM-9X35 Module Pad Characteristics Signal Name Pin # Description Voltage Type LVDS_TX_D2P J1.44 LVDS display serial interface lane 2 – positive LVDS_TX_D2N J1.46 LVDS display serial interface lane 2 – negative LVDS_TX_D0N J1.50 LVDS display serial interface lane 0 – negative LVDS_TX_D0P J1.52...

  • Page 48: Table 14: Lvds Layout Guidelines

    4 x line width Spacing data lane-to-lane 3 x line width Table 14: LVDS layout guidelines The carrier board LVDS trace length and mismatch calculations should take into account the SOM-9X35 module LVDS bus from the SOM-9X35 module. Total Trace...

  • Page 49: Lvds Reference Schematics

    Carrier Board Design Guide for SOM-9X35 Module 4.3.2 LVDS Reference Schematics LCD_VGL LCD_VCOM LVDS_LCD_VDD 2.0mm*1.2mm*1.2mm/4PAD 0.8PF 90 OHM±25% 100MHZ TUSD05L4U LVDS_D0B_N LVDS_D0_N LVDS_D0_N [13] LVDS_D1B_N C254 C255 C256 LVDS_D0B_P LVDS_D0_P LVDS_D1B_P LVDS_D0_P [13] 0.1uF 0.1uF 0.1uF EOWS201212M900 LVDS_D2B_N LVDS_D2B_P 2.0mm*1.2mm*1.2mm/4PAD 90 OHM±25%...

  • Page 50: Mipi Csi Interface

    Carrier Board Design Guide for SOM-9X35 Module 4.4 MIPI CSI Interface The SOM-9X35 module features two MIPI CSI interfaces. Each MIPI CSI has four differential pair signals that carry data signals. 4.4.1 MIPI CSI Signal Definition The following table provides the definition of the MIPI CSI signals that are implemented in the M.2 slot.

  • Page 51: Mipi Csi Layout & Routing Recommendations

    Carrier Board Design Guide for SOM-9X35 Module Pad Characteristics Signal Name Pin # Description Voltage Type MIPI CSI1A serial interface lane 2 – negative CSI1A_L2N J1.23 MIPI CSI1 4-lane CLK- MIPI CSI1A serial interface lane 2 – positive CSI1A_L2P J1.25 MIPI CSI1 4-lane CLK+ MIPI CSI1A serial interface lane 1 –...

  • Page 52: Table 18: Mipi Csi Layout Guidelines

    3 x line width Table 18: MIPI CSI layout guidelines The carrier board MIPI CSI0 4-lane trace length and mismatch calculations should take into account the SOM- 9X35 module MIPI CSI0 4-lane bus from the SOM-9X35 module. Total Trace Length...

  • Page 53: Table 20: Som-9X35 Mipi Csi0A 2-Lane Trace & Via Delay

    Carrier Board Design Guide for SOM-9X35 Module The carrier board MIPI CSI0A 2-lane trace length and mismatch calculations should take into account the SOM- 9X35 module MIPI CSI0A 2-lane bus from the SOM-9X35 module. Total Trace Length Length Delay Delay...

  • Page 54: Mipi Csi Reference Schematics

    CSI1B_L1N 16.84 -0.47 Table 22: SOM-9X35 MIPI CSI1 4-lane trace & via delay 4.4.3 MIPI CSI Reference Schematics The carrier board must use a 24MHz Oscillator to generate the main clock to the camera module. The oscillator’s power should be supplied by the VDDIO of the camera.

  • Page 55: Figure 53: Camera I2C Bus Level Shift Reference Circuitry

    The front and rear cameras must use independent reset and power down pins. It is recommended to use an I/O on the expander to control the cameras as there are only 6 GPIOs assigned on the SOM-9X35 module’s golden finger. Ensure that the I/O on the expander is the same as the cameras' I/O level.

  • Page 56: Figure 55: Camera Power Control Reference Circuitry

    Carrier Board Design Guide for SOM-9X35 Module DOVDD 3V3_VCC C720 C721 4.7uF 0.1uF VDDIO_CAM VOUT C719 FB_VDDIO_CAM R594 59K_1% 2.2uF ETA5050V0S2F C718 56pF/X EN_VDDIO_CAM Vref=0.8V R597 [17,26] CAM_EN_POW ER C722 R596 47K_1% 0.1uF/X AVDD 3V3_VCC C685 C333 VCC_2V7 4.7uF 0.1uF...

  • Page 57: Usb Interface

    4.5 USB Interface The SOM-9X35 module features two USB interfaces (USB 2.0 Host and USB 2.0 OTG). The USB Port1 interface can only be used as a host while the USB Port0 interface can be configured as either a host or client.

  • Page 58: Usb Layout & Routing Recommendations

    System firmware download from PC by USB port0, USB port0 must be configured as Device as default. Do not pull High {USBOTG_ID pin (J2.15)} on the carrier board as it is pulled High to 1.8V on the SOM-9X35 module already.

  • Page 59: Usb Reference Schematics

    Carrier Board Design Guide for SOM-9X35 Module The carrier board USB Port0 trace length and mismatch calculations should take into account the USB Port0 from the SOM-9X35 module. Total Trace Length Length Length Delay Delay Delay Net Name Length Spec...

  • Page 60: Figure 61: Usb Port1 Reference Circuitry (Part1)

    Carrier Board Design Guide for SOM-9X35 Module USB HUB A3V3_HUB D3V3_HUB D3V3_HUB 100K_1% RESET_HUB C100 USB_P1_DM USB_P1_DM USB_P1_DP USB_P1_DP HUB_D1_N HUB_D1_N [10] to Ethernet HUB_D1_P 470K HUB_D1_P [10] RESET_HUB HUB_D2_N RESET# HUB_D2_N to 4G HUB_D2_P HUB_D2_P HUB_D3_N HUB_D3_N HUB_RREF HUB_D3_P...

  • Page 61: Sdc Interface

    Carrier Board Design Guide for SOM-9X35 Module 4.6 SDC Interface The SOM-9X35 module features a Secure Digital Controller (SDC) interface. 4.6.1 SDC Signal Definition The following table provides the definition of the SDC signals that are implemented in the M.2 slot...

  • Page 62: Figure 64: Sdc Single-Ended Trace Width And Spacing Example

    2418.60 404.16 MSDC1_CMD 2363.90 -54.70 404.38 0.22 MSDC1_DAT0 2393.46 -25.14 404.08 -0.08 Refer to 6000 MSDC1_DAT1 2393.93 -24.67 67.50 404.28 0.12 MSDC1_ MSDC1_DAT2 2366.33 -52.28 404.06 -0.10 MSDC1_DAT3 2367.25 -51.35 404.36 0.20 Table 31: SOM-9X35 SDC trace & via delay...

  • Page 63: Sdc Reference Schematics

    Figure 65: SDC reference circuitry 4.7 Analog Audio Interface The SOM-9X35 module features an Analog Audio interface. 4.7.1 Analog Audio Signal Definition The following table provides the definition of the Analog Audio signals that are implemented in the M.2 slot.

  • Page 64: Pcb Layout Requirement

    Carrier Board Design Guide for SOM-9X35 Module 4.7.2 PCB Layout Requirement • Place the Headset AU_VIN1_P/N DC block capacitor near the M.2 slot and keep the ACCDET as short as possible. • The AU_MICBIAS should be guarded by the GND on all sides and should be kept away from high power/ RF signals.

  • Page 65: Audio Analog Reference Schematics

    Carrier Board Design Guide for SOM-9X35 Module 4.7.4 Audio Analog Reference Schematics On-Board MIC 3V0_VCC C557 C559 R331 0.1uF 2.2uF 1K_1% 33pF R332 MIC1_N1 1.5K_1% Close to BB C558 MIC1_P1 BLM15AG221SN1D AU0_P FB47 C560 AU_VIN0_P 220 OHM 300mA 6.3V AU_VIN0+...

  • Page 66: Figure 69: Speaker Connector Reference Circuitry

    Carrier Board Design Guide for SOM-9X35 Module Speaker L R347 C587 2200pF 33pF SPK_P1 C589 SPK_N1 BLM15PX121SN1D SPK_LP FB53 120 OHM 2000mA SPK1_LP SPK1_LN 100pF/X C596 BLM15PX121SN1D ESD58 ESD59 SPK_LN FB54 50273-0027N-001 TLSD05CBL TLSD05CBL 120 OHM 2000mA C598 R350 C599...

  • Page 67: Gpio Interface

    Carrier Board Design Guide for SOM-9X35 Module 4.8 GPIO Interface The SOM-9X35 module features a General Purpose Input/Output (GPIO) interface. 4.8.1 GPIO Signal Definition The following table provides the definition of the GPIO signals that are implemented in the M.2 slot. All SOM- 9X35 GPIOs are 1.8V domain only, all device ports should be the same.

  • Page 68: Gpio Extender

    Carrier Board Design Guide for SOM-9X35 Module 4.8.2 GPIO Extender If the carrier board needs more GPIOs, a GPIO extender is required. GPIO Expander nINT_IOEXP2 1V8_VCC 1V8_VCC R362 15K_1% BLM15PX121SN1D EXT_INT3 3V3_VCC 1V8_IO_EXP2 FB70 120 OHM 2000mA 3V3_IO_EXP2 FB59 1V8_VCC...

  • Page 69: System Boot Interface

    BATSNS circuit to avoid loading effect from the internal PMU. • The maximum power required by the SOM-9X35 module during boot may reach up to 2.5W, a maximum current of 0.9A is required for each VSYS pin (J2.71 J2.72 J2.75).

  • Page 70: System Boot Reference Schematics

    Carrier Board Design Guide for SOM-9X35 Module 4.10.3 System Boot Reference Schematics 4V6_RTC VSYS_SUS VSYS_SUS VSYS ZFB-0805H-121NC 120 OHM 6000mA SMT0805 0.22uF 22uF 22uF 22uF 10uF 0.22uF 0.1uF 1M_1% 0.1uF 0.1uF CAP0805 CAP0805 CAP0805 CAP1206 47K_1% 5V_OTG USBOTG_VBUS -20V -9.9A...

  • Page 71: I2C Interface

    All MT8365 I2C are 1.8V domain only, all the device I2C ports should be the same. − Do not pull High the I2C Bus on the carrier board as it is already pulled High to 1.8V on SOM-9X35 module. −...

  • Page 72: Uart & Spi Interface

    If the I2C device power domain is 2.5V or 3.3V, a level shift is required. (ex. G-sensor/Touch panel) • To avoid power leakage on the I2C Bus from the SOM-9X35 module to the carrier board, a diode is required for the VDD on the level shift IC (CPU side).

  • Page 73: Uart & Spi Design Notes

    All MT8365 UART & SPI Buses are 1.8V domain only, all the device ports should be the same. Do not pull the UART & SPI Buses High on the carrier board as it is already pulled High to 1.8V on SOM-9X35 module.

  • Page 74: Mcu Interface

    Carrier Board Design Guide for SOM-9X35 Module 4.14 MCU Interface The SOM-9X35 module features an MCU interface. 4.14.1 MCU Signal Definition The following table provides the definition of the MCU signals that are implemented in the M.2 slot. Pad Characteristics...

  • Page 75: Mcu Gpio List

    1V8_RTC SGM2202-ADJYN6G/TR/X VIN_1V8_RTC VOUT 4.2uA Iq BP_1V8_RTC 2.7~36Vin 150mA Iout EN_1V8_RTC FB_1V8_RTC adjustable Vout 0.8V� C741 0.01uF/X Figure 81: SOM-9X35 MCU power supply reference circuitry MCU Burning 2211S-04G-BK-F2/X For ST-LINK/V2 RN28 STM_RST STM_RST1 STM_SWIM STM_SWIM1 1V8_RTC C326 ESD38 ESD39 ESD40 0.1uF...

  • Page 76: Button Interface

    Carrier Board Design Guide for SOM-9X35 Module PIN# GPIO# Assignment Function Battery status, Low: Low voltage<6V, High: normal, BATGD_CHG reserved STATUS_CHG Battery charge status, Low: Charging; High: Charge OK EN_Main_PWR System main power enable output, High active MCU2CPU_INT1 WDI, CPU watch dog feed, High pulse active...

  • Page 77: Button Design Notes

    Carrier Board Design Guide for SOM-9X35 Module 4.15.2 Button Design Notes • Do not pull the SYSRSTB J2.48 pin High on the carrier board as it is already pulled High to 1.8V on SOM-9X35 module. Reset Key R390 33/X [15,16]...

  • Page 78: Power Manage Interface

    The EXT_PMIC_EN1 J2.56 pin is used to keep power to devices while the SOM-9X35 module is suspended, such as USB Hub, USB to Ethernet Bridge. • The EXT_3V3_ENABLE J2.54 pin is used to turn off power to devices when the SOM-9X35 module is suspended, such as LCD, speakers, etc. 4.17 Gas Gauge Interface The SOM-9X35 module features a Gas Gauge interface to monitor the lithium polymer battery capacity.

  • Page 79: Figure 86: Som-9X35 Battery Leakage Protect Reference Circuitry

    4.17.2 Gas Gauge Design Notes • The Gas gauge sensor and calculation circuit is already included by the PMU on the SOM-9X35 module. If using a lithium-ion battery, an external circuit must be reserved for the battery current sensor and single battery voltage circuit. The battery voltage must be isolated by the P Channel MOS FET to prevent power leakage.

  • Page 80: Figure 88: 2:1 Voltage Divided Voltage Following Reference Circuitry

    Carrier Board Design Guide for SOM-9X35 Module • When a dual-cell battery is used to supply power to the carrier board, a 2:1 voltage divided circuit & voltage following circuit is required. VBAT1 VBAT1 C750 0.1uF R236 SGM8240-1AXN5G/TR Opera�onal Amplifier Bandwidth 100KHz 2.7~24Vcc...
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