Interface; C Board; D3 Board; Pwm Reference, H Saw Generating Circuit - Sony Multiscan GDM-2036S Service Manual

IC504 pin@
reference pulse
____
~~n~
____ __
BKG pulse
____
~
__
~n~
____ __
blanking waveform made
on B1 board
blanking waveform sent
from N board
blanking waveform
_se_n_t_~.J
t
~
. . . . ____ _
to Aboard
! \ L
threshold level of
A board side
Fig. 3-4.
Also, for the testing, if TPI and TP2 are short-circuited, Q509
works, and the whole raSter can be seen by being stopped the
blanking.
3-2-4. Interface
The Bl Board is equipped with A, Ml, N and the interface
function with the power board other than sync separation
circuit, blank tip pulse wave shaping circuit and blank mix
circuit. Also, for the use of EMI, the delivel)' of signals and ,
power source is performed through the EMI filter.
. 3-3. C BOARD
Video signals input' to the C board are subject to series
peaking and combined by the capacitor. Then, the top end of
the blank tip pulse is clamped again by BKG voltage
determined by RV404 and Q413 of A board.
The blanking pulse and G 1 bias voltage are mixed at 07 and
supplied to Gl grid of the CRT. A spark gap and serge
protectors are mounted on the board to return the CRT
discharge (flash-over) current to chassis ground.
GDM-2036S
3-4. D3 BOARD
3-4-1. PWM reference, H SAW generating circuit
This circuit generates H. SAW signal which is the base for the
pulse width modulation to control high voltage and H. SIZE.
IClOl (1/2) generates the SAW wave, and it feeds back to
keep the waveform level constant by ICIOl (2/2). Q103 to
Q105 are the pulse phase circuit.
First of all, the HO pulse is phased by QI03, QI04 and Q105
and becomes a vel)' slender pulse, and then it is added to the
base of QlOl. QlOl is built for resetting purposes for the
integrated circuit by IClOl (1/2).
As long as QlOl is on, the output from pin
<D
of IClOl is
clamped to the GNO level. Therefore, at evel)' IH, it
generates the SAW wave terminated to GNO. IClOl (2/2)
detects the peak of SAW wave, and it feeds back to ICIOl
(l/2) so that the peak becomes equal to the voltage of R133.
The output from pin
<D
of IClOl is sent to 2 separate routes:
one is sent through ICI04 (1/2) and to H. SIZE, the other
through ICI04 (2/2) and to the high-voltage control circuit
respectively. IC103 (1/2) and (2/2) are the buffers to detect
the peak of H. SAW. It is limited by Dl08 and 0519 so that
the controls of horizontality (H) and high voltage are
not separated beyond H. SAW.
3-4-2. Horizontal deflection circuit
. The HO pulse generated on the N board goes through Q20l
and Q202 buffers and drives T201 (HOT) by Q203. The
current amplified by HOT operates on/off functions of Q204
(H. OUT) and high voltage pulse is generated at Q204
collector by the deflection yoke, damper diode 0202 and the
resonance capacitor C205, which causes SAW wave current
running through the deflection yoke. Also, Q204 collector
pulse is voltage divided by C206 and C207 and then sent to
the N board where AFC loop is formed.
H. SIZE and pin signal from the N board are amplified after
input into IC301 (l/2). These amplified signals are compared
with H. SAW at IC20l (l/2), go through Q218 and Q219 as
PWM wave, and ,are finally provided into FET Q217 gate.
Q217 makes a switching of +8, controls the power source of
horizontal deflection circuit and provides a desired H. SIZE
and pin cushion correction.
T202 is the +8 choke for horizontal deflection and also forms
the boost circuit of +B voltage by 0222 and C210 and the
power source for H. center circuit by 0209 and 0210. Q213
to Q216 are the transistors for H. center voltage control; and
they change the electric potential of bases depending on the H.
center signal going through IC301 and Q102 and provide the
voltage to the
S-sh~ed
capacitor through HCC.
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