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Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.5.1
Video Application
S ID E A V
D M M I c o n n e c to r
P C V G A
H D M I2
H D M I1
"Block diagram video processing" shows the input and output
signals to and from the Trident Video Processor in AP/LATAM
applications.
During analogue reception, a CVBS signal coming from the
analogue front-end is fed to the video processor via pin
CVBS1. No digital reception (DVB-T) reception is foreseen in
AP region. However, an internal DMMI connector is
implemented for future digital reception applications in
combination with IBO. CVI_DTV_SEL is a control signal from
the microprocessor. When this signal is LOW, then the MUX
passes the CVI1 YPbPr input signal to the Trident Video
Processor. When this signal is HIGH, then the YPbPr input
signal coming from the DMMI connector is passed to the video
processor. Currently, this signal is always LOW since no IBO is
used.
The video processor also interfaces the AV1 and Side AV
input, CVI2 (HD), VGA(PC), HDMI1 & 2. A cinch output
connector for Monitor output is foreseen.
9.6
Memory addressing
Figure "Memory block diagram" shows the interconnection
between the microprocessor, the FLASH memory, the Trident
Video Processor and the SDRAM.
A n a lo g u e
C V B S _ R F
F ro n t E n d
S C 2 _ Y _ C V B S _ IN
S C 2 _ C _ IN
A V 1
F R O N T _ Y _ C V B S _ IN _ T
F R O N T _ C _ IN _ T
C V I_ D T V _ S E L
IB O _ R _ IN
D M M I Y P b P r IN
IB O _ G _ IN
M U X
C V I Y P b P r
IB O _ B _ IN
C V I1
IB O _ C V B S _ IN
H D _ Y _ IN
H D _ P B _ IN
C V I2
H D _ P R _ IN
S C 1 _ R _ IN
S C 1 _ G _ IN
S C 1 _ B _ IN
P C _ V G A _ H
P C _ V G A _ V
H D M I_ Y (0 :7 )
H D M I_ C b (0 :7 )
H D M I_ C r(0 :7 )
H D M I
D e c o d e r
Figure 9-6 Block diagram video processing
C V B S 1
P R _ R 3
F S 2
Y _ G 3
C
P C _ R
P C _ G
P C _ B
T r i d e n t
F S 1
Video Processor
SVP CX32
Y _ G 1
P B _ B 1
C V B S
P R _ R 1
C V B S _ O U T 2
P R _ R 2
Y _ G 2
P B _ B 2
A IN _ H S
A IN _ V S
G_16860_061.eps
7311
Reneas
micro-
processor
CS/WR/RD
7202
A[0:7]
Trident CX
Figure 9-7 Memory block diagram
Control signals CPU_RST, WR, RD and CE, address lines
A[0:19] and data lines D[0:7] are used for transferring data
between the microprocessor (item 7311) and the flash memory
(item 7310). Control signals CS, WR and RD, address lines
A[0:7] and data lines D[0:7] are used for transferring data
between the Trident Video Processor (item 7202) and the
microprocessor (item 7311). Control signals CX_BA0,
CX_BA1, CX_MCLK, CX_CLKE, CX_CS0, CX_RAS, CX_CAS
and CX_WE, address lines CX_MA[0:11] and data lines
DQ[0:15] are used for transferring data between the Trident
Video Processor and the SDRAM ICs (items 7204 and 7205).
LC7.1A LA
9.
C IN C H M o n ito r o u t
310107
7310
CPU_RST/WR/RD/CE
A[0:19]
Flash Memory
D[0:7]
D[0:7]
CX_BA0/BA1/MCLK/
CLKE/CS0/RAS/CAS/WE
CX_MA[0:11]
DQ[0:15]
CX_BA0/BA1/MCLK/
CLKE/CS0/RAS/CAS/WE
CX_MA[0:11]
DQ[16:31]
EN 93
1MB
7204
8MB
SDRAM
7205
8MB
SDRAM
G_16860_062
220207
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