IBM System/370 145 Manual page 79

A
pag€:
t,able has one entry for each page in the particular segment
the page table describes. For
Cl
64K segment, there are 32 or 16 entries
in a page table depending on whE~ther a 2K or a 4K page is used,
respectively. A page table entry is two bytes in size. It contains the
12,(for a 4K page) or 13 (for a 2K page) high-order bits of the real
storage address of the page frame that is currently allocated to the
virtual storage page that the page table entry describes. Each page
table entry also contains an invalid bit to indicate whether the entry
can be used for translation. The invalid bit is on when a virtual
storage page does not have real storage currently allocated to 'it. A
translation exception occurs during the translation procedure if this
invalid bit is on.
Segment and page table format~s and entries used for address
translation are shown in Figure 15.10.2. In effect, the segment and
page tables define the relations:hip between virtual and real storage at
any given time. The segment t.ahle reflects the current size of virtual
storage, which must be a mUltiple of the segment size (64K for IBM-
supplied support), and the locat,ion of required page, tables. The
segment table also indicates,
by'
means of its invalid bits, which
segments of virtual storage are currently allocated and have a page
table available. The page tables indicate, via their invalid bits,
which virtual storage pages currently have a page frame allocated and
the location (real storage address) of these page frames.
In DOS/VS and OS/VS1 environments, segment and page tables are
established at system initialization. Page tables are modified during
system operation by control prog:r:am routines to reflect the current
allocation of real storage to vi,rtual storage so that address
translation can take place. In.an OS/VS2 environment, in which virtual
storage as well as real storage is dynamically allocated and
deallocated, the segment table constructed during IPL is modified as
required to reflect the allocation of virtual storage, and page tables
are created and destroyed as nec1essary.
Address Translation Process
A translation request is eith4er explicit or implicit. Explicit
translation is invoked via execu1t.ion of the LOAD REAL ADDRESS
instruction. Implicit translation is invoked to translate all
instruction and data addresses contained in other instructions.
Implicit address translation takE~S place during instruction execution.
'rhe details of the translation process are given in Figure 15. 10.3.
The procedure consists of a two-level, direct address table lookup
operation. Any type of translation exception causes a program
interruption and termination of t:he hardware translation process. The
CPU cannot be disabled for translation exception interruptions. Segment
and page translation exceptions t:hat occur after an explicit translation
request (LOAD REAL ADDRESS instruction) are indicated via the condition
code setting instead of via an interruption.
Translation Lookaside Buffer
When the Model 145 operates with OAT specified, additional CPU time
is required to perform the address translation process. In the Model
145, a translation lookaside buff'er (TLB) is implemented to eliminate
address translation time when possible.
The TLB contains a set of eight associative registers. Each register
has two fields. The segment and page field can contain the high-order
address bits of a recently translated virtual storage address. The real
address field contains the 12 or 13 high-order address bits of the page
frame currently assigned to the virtual storage page. Every time a
virtual storage address is translated during instruction execution, the
A Guide to the IBM System/310 Model 145
69