Data Representation Used In Model 145 Processor And Control Storage; Data Representation Used In Models 30 And 40 Processor; Storage And In The Model 145 In Other Than Processor; And Control Storage - IBM System/370 145 Manual

Doubleword - 8 bytes - 72 bits
Doubleword - 8 bytes - 72 bits
----
...............
---...
-
~
---
[
8 bits
8 bits
64 Data Bits of
64 Data Bits
of
ECC code ECC code
\ Storage Address is a Multiple of
a
Figure 50.10.1. Data representation used in Model 145 processor and
control storage
Doubleword - 8 bytes - 72 bits Doubleword - 8 bytes - 72 bits
~~------
....
---------
---
---
(
I (
Jl
,
8 Data Bits
1' ' '
8 Data Bits
1*
8 Data Bits 1*
8 Data Bits 1-
((
(
~
II
-
-
----------
I
~
Byte 8 Byte 1 Byte 8 Byte 1
*Parity Bit
Figure 50.10.2. Data representation used in Models 30 and 40 processor
storage and in the Model 145 in other than processor
and control storage
One
Eee
mode bit controls machine check interruptions for
intermittent processor storage single-bit corrections. It can be set to
full recording mode to allow an interruption after each correction so
that error logging can occur (if the control register mask bit is on
also) or to quiet mode to disable the CPU for interruptions after
single-bit processor storage corrections occur (without regard for the
control register mask bit setting). The other two
Eec
mode bits control
machine check interruptions for control storage single-bit corrections.
Three modes are possible: full recording or quiet mode~ as described for
processor storage, and threshold mode. When threshold mode is in
effect, a machine check interruption is taken after a certain number of
single-bit control storage corrections have occurred in a given time
interval. (These threshold values are hardwired.> When the threshold
is exceeded, the hardware automatically establishes quiet mode for
control storage single-bit corrections.
If a machine check interruption is taken after correction of a
single-bit storage error, identification of the failing processor or
control storage address and bit in error is provided in·a fixed storage
area (discussed in the machine check interruption explanation).
When a double- or multiple-bit storage error involving a CPU
operation is detected, the microinstruction retry procedure is
initiated. If a single-bit, instead of a doUble- or multiple-bit error
results from one of the retries, the error is corrected and system
operation continues as described above for a single-bit error. If the
188
A Guide to the IBM System/370 Model 145