IBM System/370 145 Manual page 204

The SC bit in the stored machine check code (bit 11) is used
together with the SR bit to indicate that the ECC hardware
corrected a single-bit intermittent processor storage error and
passed correct information about the error to the
cpu.
The
failing processor storage address is stored in locations 248-251.
The region code indicates the bit corrected and whether or not
the error was intermittent. When a control storage error occurs,
the failing control storage address, the bit corrected, and
whether the error was intermittent are indicated in the region
code. When the interruption occurs because the single-bit
control storage threshold has been exceeded, this fact is also
indicated in the region code. Validity bits 24 and 25 indicate
that the failing storage address and region code, respectively,
have been stored correctly. Only error recording is required for
this interruption.
• Interval Timer Damage. This interruption occurs if PSW bit 13
and the external mask bit are on. It indicates damage to the
timer. programmed validation procedures and error logging are
required.
• Timing Facilities Damage. This interruption occurs if both PSW
bit 13 and the external mask bit are on. The CD bit in the
stored machine check code (bit 4) is used to indicate that an
error occurred in the time of day clock that renders the c10ck
invalid. Once this invalid indication has been given, subsequent
STORE CLOCK instructions cause the condition code in the current
PSW to indicate the fact that the clock is invalid. Error
logging is required as a result of clock failure. This
interruption also occurs if a STORE CLOCK COMPARATOR or a STORE
CPU TIMER instruction is issued and the addressed timing feature
has an error condition.
Exigent Machine Check Interruptions
194
Exigent machine check interruptions are as follows:
• Instruction processing Damage. This interruption occurs if PSW
bit 13 is on. The PD bit in the stored machine check
interruption code (bit 1) is used to indicate that an error
occurred during the execution of the instruction indicated by the
machine check old PSW. The error was either a double-bit
processor or control storage failure, a storage protect key
failure, or a CPU error that was unretryable or that could not
be
corrected by microinstruction retry hardware.
If a double-bit processor or control storage failure caused the
interruption, the address of the failing storage area is
indicated in locations 248-251 or 252-253, respectively. The SE
(storage uncorrected) bit is turned on for a processor storage
error. Byte 3 of the region code indicates a control storage
error. The KE bit in the machine check code (bit 18) is set on
when a storage protection failure occurs. The processor storage
block affected is indicated in the failing storage address field
(248-251).
If an unsuccessfully retried CPU failure caused the interruption,
the backed-up bit in the machine check code (bit 14) indicates
the extent of the damage that
occur~ed,
if any. If the backed-up
bit is on, i t indicates that no source data has been changed and
that the PSW registers and storage reflect the valid state that
existed at the beginning of the instruction. (For a CPU error,
an extended logout is generated on the first and eighth
unsuccessful retry.)
A Guide to the IBM System/370 Model 145