Storage And The Console File; Control And Processor (Main) Storage - IBM System/370 145 Manual

period half as large as that of the time of day clock and the same
resolution of one microsecond. When both the CPU timer and the time of
day clock are running, the stepping rates of the two are synchronized
such that they are stepped at exactly the same rate.
The CPU timer is set to zero at initial program reset, and the SET
CPU TIMER privileged instruction is provided to place an interval of
time in the CPU timer. The STORE CPU TIMER privileged instruction can
be used to obtain the current CPU timer value. The CPU timer decrements
every microsecond. If the external interruption summary mask bit in the
current PSW and the CPU timer subclass mask bit in control register 0
are on, an external interruption occurs whenever the CPU timer value is
negative (not just when the timer goes from positive to negative),
indicating that the time interval has elapsed. The CPU timer decrements
when the CPU is executing instructions (including retry operations) and
while the CPU is in the wait state. The CPU timer is not decremented
when the system is in the stopped state.
While providing essentially the same function as the interval timer
at location 80, the CPU timer provides advantages over the interval
timer as follows. Task processing intervals of less than 3.3
milliseconds can be more accurately measured because of the one-
microsecond resolution of the CPU timer. A pending CPU timer
interruption is reset when a SET CPU TIMER instruction is used to set a
positive value in the CPU timer, eliminating the need to take an
interruption in order to reset the CPU timer, as is required for the
interval timer. In addition, the amount of timing facilities processing
required during a task switch is reduced. This results from the fact
that the format of the time of day clock and the CPU timer are the same.
Conversion of doubleword time of day clock values to single word
interval timer values is eliminated, and timer queues can be structured
such that little of the processing currently required during a task
switch, when the interval timer is used, is necessary.
10:1~ STORAGE AND THE CONSOLE FILE
CONTROL AND PROCESSOR (MAIN) STORAGE
A significant new storage feature of the Model 145 is reloadable
control storage (RCS) for microprogram residence. The use of writable
storage for control functions adds to the advantages of using a read-
only storage instead of conventional circuitry.
As implemented in the Model 145, use of RCS instead of read-only
storage results in system cost savings and provides improved
serViceability and additional system functions:
24
• f;ystem cost savings result because the total amount of control
f;torage required is reduced. Fixed control storage addresses for
each specific microcode function are not required. Since control
~.torage
is reloadable, the microcode required to support the
hardware features of a specific system configuration can be
efficiently packed in available control storage when the given
system microcode is customized. In addition, all microcode for a
system need not be resident at all times. For example, different
versions of microcode for a given system containing different
features can be loaded when required, and diagnostics overlay normal
system microcode when they are needed. Furthermore, the fact that a
single writable storage can
be
and is used for both control and
processor storage helps achieve the price performance goal of the
Model 145.
A Guide to the IBM System/370 Model 145