IBM System/370 145 Manual page 29

Program Interruption for
~
set §Jrstem Mask Instruction
When a Model 145 is operating in EC mode w execution of the SET SYSTEM
MASK instruction is under the control of the SSM mask bit in control
register
O.
When the SSM mask bit is onw an attempt to execute an SSM
instruction causes a program
intE~rruption
without execution of the SSM
instruction. When the SSM mask bit is off. SSM instructions are
executed as usual.
This interruption is implement:ed to enable existing programs that
were written for System/360 model.s or for System/310 BC mode of
operation to execute correctly iIll EC mode without modification of the
system mask field addressed by eJi:isting SSM instructions. When an SSM
interruption occurs w the contents: of the BC mode format system mask
indicated by the SSM instruction can be inspected and the appropriate EC
mode mask bits can then be set bj' an SSM simulation routine.
Program Event Recording
Program event recording (PER), a standard feature on the Model
145
w
is designed to assist in program debugging by enabling a program to be
alerted to any combination of the following events via a program
interruption:
• successful execution of any type of branch instruction
• Alteration of the contents of the general registers designated by
the user
• Fetching of an instruction from a processor storage area defined by
the user
• Alteration of the contents of a processor storage area defined by
the user
The PER feature can operate on.ly when EC mode is in effect and the
PER maskw bit 1 of the current PSlil w is a one. Control register 9 (bits
o
to 3) is used to specify which of the four PER event types are to be
monitored. A PER program interruption is taken after the occurrence of
an event only if both the PER masl~ bit and the respective event mask bit
in control register 9 are on. Coutrol register 9 (bits 16 to 31) also
specifies which of the 16 general registers are to be monitored if
monitoring of this event is specijcied,. Control registers 10 and 11
indicate the beginning address and the ending address w respectivelyw of
the contiguous processor storage .area that is to be monitored for
instruction fetching and/or alteration.
When an event that is being mOilitored is detected w PER hardware
causes a program interruption, if the PER mask bit is on, and the
identification of the type of event is stored in the fixed storage area
(location 150). The address of the instruction associated with the
event is also stored (locations lS3 to 155). Program event
interruptions are lost if they Oc(:ur when the PER mask bit or the
particular event mask bit is off. In the Model 145
w
instruction
processing time is increased when the PER facility is operative.
If dynamic address translation mode is also specified when PER is
active w virtual storage addresses instead of real storage addresses
(discussed in Section 15) are plac:ed in the control registers to monitor
references to a contiguous virtual storage area.
A Guide to the IBM System/310 Mode~l 145 19