IBM System/370 145 Manual page 202

Table 50.10.1 lists the machine check types defined for the Model
145. They are described in the discussion that follows. The mask bits
used to enable or disable the CPU for interruptions for each type are
indicated and the setting of the machine check and region codes are
discussed. PSW bit 13 and two other mask bits are used to enable and
disable the CPU for ma~hine check interruptions. The recovery mask
(R)
and external mask (E) bits are contained in control register 14 and
operate subject to PSW bit 13. If PSW bit 13 is a zero, the CPU is
disabled for all machine checks. If PSW bit 13 is a one, the settings
of the two additional mask bits determine whether or not interruptions,
other than Instruction Processing Damage and System Damage, wil1
be
taken (refer to Figure 50.10.4).
Table 50.10.1. Model 145 machine check interruptions
Mask Bit(s}
psw13
and R
PSW 13
and E
PSW 13
and E
PSW 13
PSW 13
Interruption Type and Cause
System Recovery
-CPU error corrected by retry
-Intermittent single-bit
processor or control
storage error corrected
Interval Timer Damage
Timing Facilities Damage
-Time of day clock
-Clock comparator
-CPU timer
system Damage
-Irreparable hardware
malfunction
Instruction Processing Damage
One of the following
occurs during instruction
execution:
-Unretryable CPU error
-Uncorrectable CPU error
-Double-bit processor or
control storage error
-Storage protect key failure
Machine Check Condition
Repressible
Repressible
Repressible
Exigent
Exigent
Repressible Machin~ Check Interruptions
192
Repressible machine check interruptions are as follows:
- System Recovery. This interruption occurs if both PSW bit 13 and
the recovery mask bit are on. It is caused by a successfu1
microinstruction retry or a single-bit intermittent processor or
control storage error correction.
The SR bit in the stored machine check code (bit 2) is used to
indicate successful hardware recovery. When the SR bit is on
without another recovery bit, an error. has occurred in the normal
functioning" of the CPU and the CPU operation has been retried
successfully
by
microinstruction retrj" hardware. CPU extended
logout data is generated after the first and eighth retry.
A Guide to the IBM System/370 Model 145