Digital Block Diagram (1/2) - Panasonic DMR-UBS80EG Service Manual

11.5. Digital Block Diagram (1/2)

(DMR-UBS80EG)
TU8000
+12.3V
(DVB-S/S2 TUNER)
LNB A 2
LNB B 1
IC8001
(DEMODULATOR)
DISEQC OUT
6
TS DATA0 15
Q OUT A 14 39 S ADC QP
TS CLK 14
I OUT A 13 37 S ADC IP
TS SYNC 13
TS VAL 12
IN1
AGCA 11 30 MP D
SDA NOST 11
SDA 8 45 SDA MAST
SCL NOST 10
LNB
SCL 9 46 SCL MAST
RESETB 31
IN2
IC8002
(DEMODULATOR)
DISEQC OUT 6
45 SDA MAST
TS SYNC 13
46 SCL MAST
TS VAL 12
15
TS DATA0
Q OUT B 5 39 S ADC QP
TS CLK 14
I OUT B 6 37 S ADV IP
SDA HOST 11
SCL HOST 10
AGCB 3 1 MP A
RESETB 31
(DMR-UBS90EG)
VIDEO REC SIGNAL
TU8500
VIDEO EE SIGNAL
(DVB-S/S2 TUNER)
VIDEO PB SIGNAL
AUDIO REC SIGNAL
AUDIO EE SIGNAL LNB A 2
AUDIO PB SIGNAL
IC8501
(DEMODULATOR)
Q OUT A 14 39 S ADC QP
I OUT A 13 37 S ADC IP
LNB IN2
AGCA 11 30 MP D
SDA 8 45 SDA MAST
SCL 9 46 SCL MAST
IC8701
IC51001_PXS2
(LNB P.SUPPLY CONT.)
(HD DEC/ ENC/ CPU/
GFX PROCESSOR/DDR2-IF/RTSC/
SCL 7
20 VOUT
AV CORE/GRAPHICS)
SDA 8
17 VCC
DSQIN 22
IC8801
(LNB P.SUPPLY CONT.)
VCC SCL 7
17
SDA 8
20 VOUT
DSQIN 22
CH0DATA
AG35
CH0DATA
CH0CLK
AG34 CH0CLK
CH0PSYNC
AF35 CH0SYNC
CH0VAL
AF33 CH0VAL
G SDA1 B
AD34 SDA1
G SCL1 B
AD32 SCL1
XFE SET
AK5 XFERST
CH1PSYNC
AG33 CH1PSYNC
CH1VAL
AH34 CH1VAL
CH1DATA
AF34 CH1DATA
CH1CLK
AF36 CH1CLK
RESETB 31
SCL HOST 10
SDA HOST 11
DISEQCOUT 6
CH2DATA
TS DATA0 15
CH2CLK
TS CLK 14
CH2PSYNC
TS SYNC 13
CH2VAL
TS VAL 12
(DMR-UBS90EG)
(SD CARD SLOT)
P56101
7 G_SD0DAT0_A
DAT0
8 DAT1 G_SD0DAT1_A
P58805
9 DAT2 G_SD0DAT2_A
TX+
17
1 G_SD0DAT3_A
DAT3
BD TX- L56003
16
5 CLK CKG_SD0CLK_A
DRIVE RX-
14
RX+ L56004
13
IC56302
(MEMORY)
CS 1
DO 2
DI 5
CLK
P20002 P20001 P58810
TX+
6 2
TX-
HDD 5 3
RX-
3 5
RX+
2 6
IC59001
JK59001
(ETHER CONTROLLER)
(LAN PORT)
1 TX0+
7 TXP
TX0-
2
6 TXM TXD0-1, RXD0-1
TX1+ T59001
3
5 RXP
TX1 -
6
4 RXM
MDIO
11
MDC 12
CRSDV 18
REFCLK 19
RXER 20
INTRP 21
TXEN 23
32
RST
+12.3V
TU8000
(DVB-S/S2 TUNER)
LNB B 1
IC8001
(DEMODULATOR)
Q OUT A 14 39 S ADC QP
DISEQC OUT 6
TS DATA0
I OUT A 13 37 S ADC IP 15
TS CLK 14
TS SYNC 13
AGCA 11 30 MP D
TS VAL 12
SDA 8 45 SDA MAST
SDA NOST 11
SCL 9 46 SCL MAST
SCL NOST 10
LNB IN1
RESETB 31
IC8002
(DEMODULATOR)
45 SDA MAST
TS SYNC 13
46 SCL MAST
12
TS VAL
Q OUT B 5 39 S ADC QP
TS DATA0 15
TS CLK 14
I OUT B 6 37 S ADV IP
SDA HOST 11
SCL HOST 10
AGCB 3 1 MP A
RESETB 31
89
IC51001_PXS2
(HD DEC/ ENC/ CPU/
GFX PROCESSOR/DDR2-IF/RTSC/
AV CORE/GRAPHICS)
G_PX2_SD0DAT0
G34 SD0DAT0
G_PX2_SD0DAT1
E34 SD0DAT1
G_PX2_SD0DAT2
G32 SD0DAT2
G_PX2_SD0DAT3
F32 SD0DAT3
CKG_PX2_SD0DCLK
SD0CLK
F33
IC59001
(ETHER CONTROLLER)
34 TXP SSTXP 20 G35
USB2RXP
SSTXN 19 F35 USB2RXN
33 TXN SSRXN 22 H35 USB2TXN
SSRXP 23 J35 USB2XP
31 RXN
30 RXP
DM 13 H34 USB2DN
L56301
15 USB2DP
DP F34
6 GPIO(3)
2 GPIO(0)
5 GPIO(2)
6 3
GPIO(1)
TX+
C33
SATATXP
L56001
TX-
SATATXM
D33
RX-
C31 SATARXP
RX+
D31 SATARXM
TXD0-1, RXD0-1
AU1 MDIO
AR1 MDC
AT6 RGMII RXCTL
AV3 RGMII RXCLK
AT5 RGMII RXD2
AT1 MDIO INTL
AR8 RGMII TXCTL
AU2 PHYRSTL
IC8701
(LNB P.SUPPLY CONT.)
SCL 7
20 VOUT
SDA 8
17 VCC DSQIN 22
IC8801
(LNB P.SUPPLY CONT.)
SCL 7
17 VCC
SDA 8
VOUT
20 DSQIN 22
CH0DATA
AG35
CH0DATA
CH0CLK
AG34 CH0CLK
CH0PSYNC
AF35 CH0SYNC
CH0VAL
AF33 CH0VAL
G SDA1 B
AD34 SDA1
G SCL1 B
AD32 SCL1
XFE SET
AK5 XFERST
CH1PSYNC
AG33 CH1PSYNC
CH1VAL
AH34 CH1VAL
CH1DATA
AF34 CH1DATA
CH1CLK
AF36 CH1CLK
AV35 CH2DATA
AV37 CH2CLK
AV36 CH2PSYNC
AU35 CH2VAL
DMR-UBS80EG/UBS90EG
Digital Block Diagram (1/2)