Negative Transients At High Side Reference (Pin Vsx); Bootstrapping; Figure 9 Structure Of The Lowside Gate Drive Section; Figure 10 Bootstrap Circuit For One Halfbridge A) 6Ed003L06-F2 And 6Ed003L02-F2 B) Others - Infineon EiceDRIVER 6ED Series Application Note

Figure 9 Structure of the lowside gate drive section
3.5.3

Negative Transients at High Side Reference (pin VSx)

The 6ED family - 2nd generation is very robust against negative transient voltages thanks to the inherent oxide
insulation of the SOI-technology. Therefore, the minimum voltage at the pins VSx is specified to -50 V for a
period of time of 500 ns. This duration is long enough to cover the usual requirement for this stress in drives
applications. However, it must be the target of any design to avoid such negative voltages at all.
Parasitic inductances can induce voltages, so that the potential at pins VS1, VS2 or VS3 becomes negative in
respect to pin VSS. It is a well known failure mechanism of other driver IC technologies, that these negative
voltages force current through the substrate material. The substrate currents can lead to a latch of the high side
gate driver, which is then insensitive to any control signal. The result is, that the IGBT are operated in short
circuit, which leads to excessive power dissipation and also to system breakdown.
The negative voltage can also increase the pulse current through the external or internal bootstrap diode and
may lead to damage. The design target is therefore to avoid such negative transient voltage at all or to keep at
least the absolute maximum ratings.
3.6

Bootstrapping

Bootstrapping is a common method of pumping charges from a low potential to a higher one. With this
technique a supply voltage for the floating highside sections of the gate drive can be easily established
according to Figure 10. This circuit is shown for one of the three half bridges. The current limiting resistor R
may be connected to each of the three bootstrap diodes of the three halfbridges.
a)
R D
Lim
v
FBS
VCC
Gate
Drive
C
IC
VCC
GND
Figure 10 Bootstrap circuit for one halfbridge
a) 6ED003L06-F2 and 6ED003L02-F2
b) others
The first pulse of transistor T2 will force the potential of pin VS to GND. The existing difference between the
voltage of the bootstrap capacitor V
current iBS is a pulse current and therefore the ESR of the capacitor CBS must be very small in order to avoid
losses in the capacitor, that results in lower lifetime of the capacitor.
Application Note
AN-EICEDRIVER-6EDL04-1
Bootstrap diode (opt.)
HV LEVEL-
SHIFTER
BS
i
BS
V
Bus
VB
C
T1
BS
HO
D1
VS
T2
LO
D2
and V
CBS CC
6ED family – 2nd generation
LATCH
DRIVER
UVLO
b)
VCC
C
VCC
GND
results in the charging current i
14
6ED family - 2nd generation
Technical Description
VB3
HO3
VS3
R D
VB
Lim
BS
C
T1
BS
HO
Gate
VS
Drive
T2
IC
LO
into the capacitor C
BS
Rev. 1.3, 2014-03-23
Lim
V
Bus
D1
D2
. The
BS