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3.5
Gate drive section
3.5.1
Low side gate drive
The lowside gate drive sections contain FET in push-pull configuration. The typical on-state resistance of them
is approximately R
DS(on),p
channel) according to Figure 8. This results in a typical turn-on current of I
current of I
= 375 mA. The R
O-
their test conditions.
There is a levelshift structure inlcuded in the 6ED family - 2nd generation in order to allow the potential at pin
COM to be negative referenced to pin VSS without forcing substrate current in the IC. This is important,
because instantaneous diode forward voltage drop of the low side freewheeling diode can be larger than -0.7 V.
Please note here, that this levelshift is not correlated with negative voltage transients of pin VSx referenced to
COM.
DELAY
Figure 8
Structure of the lowside gate drive section
The output pins LOx are clamped to the supply voltage VCC of the IC via the reverse diodes of the FET. This
prevents the output pins from excessive pulse voltages, which may be coupled into the gate track. There is also
an internal zener clamp of the push-pull circuit between COM and VCC.
3.5.2
High side section
The high side gate drive section is shown in Figure 9. The control signal passes the high voltage level shift
section and is stored in the gate drive flipflop-latch. The incoming signal as well as the output gate drive signal
are clamped internally by integrated diodes to the reference voltage (pin VSx) and the bias voltage (pin VBx),
which is identical to the low side sections.
Please note, that there is a parasitic connection from each high side to the low side control area in case of the
types 6ED003L06-F2 and 6ED003L02-F2. It must be guaranteed by the design of the induvidual application,
that there are no negative voltages lower than -50 V referred to VSS at pin VS1, VS2 or VS3, which last longer
than 500ns according to the maximum rating of the datasheet of 6ED family - 2nd generation.
All other members of the 6ED family – 2
section 3.6 for further information about the integrated bootstrap diode.
Application Note
AN-EICEDRIVER-6EDL04-1
= 35 for the turn-on FET (p-channel) and R
-values can easily be calculated by means of the parameter V
DS(on)
VCC
VSS / COM
LEVEL-
SHIFTER
VSS
nd
generation contain an integrated bootstrap diode. Please refer to
DS(on),n
6ED family – 2nd generation
35
R
ON
I
O
PMOS
+
NMOS
I
O
11
R
-
ON
13
6ED family - 2nd generation
Technical Description
=11 for the turn-off FET (n-
= 165 mA and a typical turn-off
O+
R
G
LOx
COM
Rev. 1.3, 2014-03-23
, V
and
OL
OH
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