Table of Contents
Advertisement
3.2.1
Highside input pins (HIN), Lowside input pins (LIN)
a)
5 V
I
LIN
I
HIN
HINx
LINx
V
Figure 3
Control input pin structure
a) negative logic
b) positive logic
All gate control input pins are equipped with an integrated zener clamp which is activated, when the input signal
is higher than 5.25 V according to Figure 2. It must be guaranteed by application design, that these zener
diodes are not overstressed by excessive voltages larger than V
trigger is typically V
= 2.1 V and the LOW level is V
IH
to LSTTL- and CMOS-levels, so that the 6ED family - 2nd generation is compatible to common microcontroller
output pins. Some
competitor's
the connectivity to the microcontroller is a major concern. Electromagnetic interference may cause distorsions of
the control signals, so that a RC-filtering of the input pins can improve the signal integrity of the system. The RC
filter must not distort the control signal, so that the edges are still steep. A good design is therefore to use a
resistor of 100 and a capacitor of 1 nF.Please note here, that the impedance of the RC filter must follow the
I/O-pin specifications of the microcontroller, so that the controller can drive the RC-filter sufficiently.
A) of Figure 3 shows the input structure of the negative logic. The integrated pull-up resistor pulls the inputs to
HIGH, if the pin is floating or driven from a high impedance source. The maximum current out of each /HIN- or
= 200 μA, if applying a LOW signal. An external additional pull up resistor can help to
/LIN-pin is I
= I
LIN-
HIN-
obtain a reliable and precise control signal. B) of Figure 3 presents the structure of positive logic. The pull down
resistor has a value of typical 5 k. The input bias currents with I
compared to the negative logic
The input noise filter suppresses short pulses and prevents the driven power transistor from excessive switching
losses due to linear operation of the switching transistors. The input noise filter time at any control input LIN or
HIN is typically t
=270 ns. This means, that an input signal must stay on its level for this period of time in
FILIN
order that the state change is processed correctly according to Figure 4. However, it is recommended to stay
above a minimal pulse duration of 1 μs.
3.2.2
Enable pin (EN)
The signal applied to pin EN controls directly the output sections. All outputs are set to LOW, if this signal is
lower than V
= 1.3V typically and operation is enabled with signal levels higher than typical V
EN-
internal structure of this pin is similar as b) in Figure 3 except for the switching levels of the Schmitt-Trigger and
the pull-down resistor has a value of typ. 75 k. The typical propagation delay time from EN to the output
sections is t
= 780 ns.
EN
The IC is steadily enabled, when the EN pin is pulled up to VDD (i.e. +5V / +3.3V). It is not recommended to pull
this pin up to VCC (i.e. +15V), because this may lead to an excessive power dissipation in the input structure of
this pin and could destroy the IC. This pin can be used as a redundant way to shut down the application in case
that a (double) failure occurs or a first shut down mechanism fails by incident.
Application Note
AN-EICEDRIVER-6EDL04-1
6ED-family
V
cc
2nd gneration
V
; V
IH
IL
INPUT
NOISE
FILTER
=10.5 V
Z
components do not provide the full compliance to these voltage levels, so that
6ED family - 2nd generation
b)
HINx
LINx
= 5.8 V. The HIGH levels of the input Schmitt-
IN
= 0.9 V. This setting of levels provides a full compliance
IL
= I
LIN+
HIN+
10
Technical Description
6ED-family
V
cc
2nd gneration
I
V
; V
LIN
IH
IL
INPUT
I
HIN
NOISE
FILTER
V
=10.5 V
Z
= 660 μA are therefore higher
= 2.1 V. The
EN+
Rev. 1.3, 2014-03-23
Advertisement
Table of Contents
