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Remove the microprocessor from its socket.
2.
Connect the pod
3.
to
the
power
for
and
15
+5V,
second mainframe and shielded cable to provide self test power to the
pod.
Connect
4.
mainframe, then connect the second pod
processor socket of the pod under test.
not apply
Do
between second pod and inoperative pod.
references to data
A ll
in hexadecimal
are
guide
Refer to the Theory of
Section
to troubleshoot an inoperative pod using the following steps
7
guide:
Reset the pod by
1.
cable connector located on the upper PCB assembly.
Perform
2.
default address. Instead, set the BUS test address to
Perform
3.
Perform
4.
ROM checksum
in Table
5—5.
Check the
5.
U23) as follows:
Perform
a.
of
lines
I
/
data
write
under
test
connector normally
for
and pin
pin
21
-5V,
mainframe to a second pod. Apply power to the
a
CAUTION
remove any power
or
NOTE
and
addresses
notation.
Section
Operation
in
momentarilyshorting
a BUS test. Because of a
RAM test. The RAM addresses are listed in Table
a
a ROM test. The ROM addresses are listed in Table
returned
by a Quick
output operation
operation to
a write
0
A
port
(PAO—PA7) as
FF.
is
to
and
+5V
-5V
power supplies. Apply
to
the mainframe;
coupled
for ground.
25
ribbon
ribbon cable connected
with
the following troubleshooting
in
and the schematic diagram in
4
pins 22 and
contention situation,
ROM
ofthe
test
of
I/O
A (contained in
port
A direction register to set
the
port
The write address
outputs.
Z8OQT
2
pins
use
If
available, use a
cable to the micro-
a
as
of the shielded
23
do not use the
2000.
5-4.
The
5-4.
ROM
pod
given
is
and
U21
all
is
2081;
5-15
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Table of Contents
Troubleshooting
