Fluke 9000A-Z80QT Instruction Manual page 47

Interface pod
Table of Contents

Advertisement

0
Address buffers,
0
Sensing latches,
Hold low circuit, U12 and associated components, to hold address lines at
0
0000 when the UUT
source/sink
0
Power
Interface Section
4-10.
UUT
Data
Buffer Ul
The
controlling the Processor Section. This disabling prevents
is
processor
for
the UUT from reaching the UUT. Conversely, the
meant
enabled by the timing circuits when the microprocessor
Section, such as, during a UUT read/ write
Processor
The direction of the
BDO—7.
function of the microprocessor RD line.
data
passing between the pod and the UUT
All
circuits; one circuit per line. Each
protection
resistor
in series with the line, and a
lOO-ohm
data
line at zero and
clip the
lines are also equipped with logic level detection circuits; one circuit per
data
The
detection
line. The
of the respective protection circuits. A series resistor at the
provides overvoltage protection.
data
lines are coupled
The
logic high if the line
each latch
to
is
driven low. The LATCH signal from the Timing Section latches the
logic levels, at the time shown in Figure 4-4, to store the logic levels representing
the state of each data
the conclusion
At
Address decoder
microprocessor.
contents
of the latches on the
contents
of the addressed latch with the intended write
between the contents of the latch and the intended
error.
and
U5
U3
U8 and
U2, U4, U6,
not accessed
is
U10 for
protection
Data Lines
-
disabled by the timing circuits whenever the micro-
is
dag:
buffer
volts.
+5
circuits consist of
a
inputs of
to
the
is
line.
of a UUT write
operation,
U7
produces the DATAEN signal to place the
data
U9
circuits
operation
controlled by the
is
fed
is
protection
of clipping diodes. The diodes
pair
series of latches coupled
latches U2 by lines
driven high, and logic low if
latch U2 are addressed by the
bus. The microprocessor compares the
data
ZBOQT
data
not
data
buffer
not
controlling the
is
via data lines
DIRIN
line, a
a series of
through
circuit consists of a
the UUT side
to
input of
each latch
The
input
LDO—7.
line
the
data
line
data.
Any difference
data
is
considered a
is
is

Advertisement

Table of Contents
loading

Table of Contents