Fluke 9000A-Z80QT Instruction Manual page 46

ZBOQT
Processormonitors
The
for mainframe
commands. The
of address
lines
A0—A7
A12-Al4 to produce
address lines
O, or Interval Timer.
I /
mainframe
The places a low on the MAINSTAT line when a command
on lines POD0-7. The
emulator
and reading
received, the
handshaking
that
to insure
4-3
no
mainframe
Each
commands causes the microprocessor to execute a
routine contained
ing
mainframe command
internal operations
necessary
example, if the mainframe command calls
microprocessormust perform
data to
ready the be written, and
command.
with the
In addition, routine
the
transmits
any response
the current condition
which reflects
transmission
of data
as shown in the lower
operate
data
lost
is during
no
The microprocessor
and HALT, a means of verifying
as
microprocessor can control
WAIT, as a means of preventing stuck UUT status lines from interfering with
Both the drive signals
pod operation.
for
the status lines are written by the
emulator.
Interface Section
4-9. UUT
Refer
to Figure 4-2. The UUT
shown in Figure
components
0
Bidirectional
0
Protection
circuits,
4-8
handshake
the
microprocessor
address
and decoder, U31. The address decoder decodes
@
the
microprocessorresponds
of
the mainframe command.
each byte
lines
operate
data
lost.
is
in ROM U2. This
by first setting the interval timer and then performing all
preparation for
in
the steps necessary
perform
actual
directs the
data
back to the mainframe, and produces a status byte
status back to
and
of
portion
the transmission process.
has the capability of software~driving control lines BUSAK
the enabling
for
microprocessor through
General
-
Interface
4-2:
data
buffer, U1
A1 A5
-
line, MAINSTAT, at
addresses
that
selects either the RAM,
signal
by addressing
as shown in the
upper portion
routine, when executed, performs the
addressing the UUT.
for
Write
a
to assemble the UUT address,
housekeeping operations associated
write and read functions of the UUT,
and UUT. During the
of the
pod
the mainframe, the handshake lines
handshake
The
Figure 4-3.
that they can be driven. Also, the
disabling of status lines BUSRQ and
or
control lines and the enable signals
the
Section includes the following
0
I / waiting
port
B,
0
I / B
port by means
is
placed
0
of the
I A
/ port
each byte
As
of Figure
correspond—
For
the UUT, the
to
that
insures
0
of the
I
/ port
B
is