Fluke 9000A-Z80QT Instruction Manual page 42

ZBOQT
Interface Section
4-4. UUT
Interface
The UUT
elements:
Data
0 and address buffers
Protection
0
circuits
0
Logic level detection circuits
data address
The and
UUT, or disabled
buffers
maintained by the timing section.
is
to the UUT contains
Each line
of a lOO-ohm series-resistor and clipping diodes. This circuit prevents over
voltage conditions from damaging pod components.
Each line to the UUT contains a
latch connected to
a
senses the level at the UUT side of the
each UUT
operation,
individually addressed and read by the Processor Section. Their contents are
then compared
with the desired results
Section
4-5.
Timing
primary function
The
either
work with the
pre—determined by the
work with one section or the
mainframe commands,permits
The Timing Section of the pod, shown in Figure
and an
arrangement
determines the time
microprocessor,
Processor
addressing the
Interface
Section
(and
microprocessorto
versa, would result in
UUT, or Vice
their
In
reset state,
Processor
of the
part
mainframe
When the
operation, the
microprocessor
value set on the interval
to prepare for
Section
UUT.
4-4
Section, shown in Figure
for
signal lines
for data,
buffers are enabled to connect the
to isolate the microprocessor from the UUT.
protection
a
detection
UUT the
the side of
protection
stores the level of the UUT line. Each latch
of the timing section
Processor Section or the UUT Interface Section
microprocessor
other
the use of only one microprocessor in the pod.
of timing circuits. The interval timer, preset by the
at
Section
(RAM,
UUT). This timing
Processor
address the
improper
the timing circuits cause the
Section, which includes an
command
issues a pod
the
sets
timer corresponds
command execution
include the following
4—1,
address, status and control lines
microprocessor
circuit. A protection
circuit. A detection circuit consists of
lOO-ohm protection
circuit, and at the conclusion of
a means of detecting UUT bus faults.
as
to cause the microprocessor
is
itself. Causing the microprocessor
during
as required
consists of an interval timer
4—1,
which the microprocessor switches from
to addressing the UUT
ROM and
I / O)
critical, since any
is
Section with addresses meant for the
operation.
microprocessor to
/0
port to
I
which calls for a UUT read or write
interval timer to a specific value. The
to the time needed by the Processor
to actually addressing the
prior
to the
Control
of the
-
circuit consists
resistor. The latch
then
is
to
at a time
to
the execution of
by the
attempt
operate as a
the mainframe.