Denon DCD-A100 Service Manual page 60

M3062LFGPGP Terminal Function
Pin No. Pin Name
1 P9_4/DA1/TB4IN
2 P9_3/DA0/TB3IN
3 P9_2/TB2IN/SOUT3
4 P9_1/TB1IN/SIN3
5 P9_0/TB0IN/CLK3
6 BYTE
7 CNVSS
8 P8_7/XCIN
9 P8_6/XCOUT
10 *RESET
11 XOUT
12 VSS
13 XIN
14 VCC1
15 P8_5/*NMI
16 P8_4/*INT2/ZP
17 P8_3/*INT1
18 P8_2/*INT0
19 P8_1/TA4IN/*U
20 P8_0/TA4OUT/U
21 P7_7/TA3IN
22 P7_6/TA3OUT
23 P7_5/TA2IN/*W
24 P7_4/TA2OUT/W
25 P7_3/*CTS2/*RTS2/TA1IN/*V
26 P7_2/CLK2/TA1OUT/V
27 P7_1/RXD2/SCL2/TA0IN/TB5IN
28 P7_0/TXD2/SDA2/TA0OUT
29 P6_7/TXD1/SDA1
30 P6_6/RXD1/SCL1
31 P6_5/CLK1
32 P6_4/*CTS1/*RTS1/*CTS0/CLKS1 FS1
33 P6_3/TXD0/SDA0
34 P6_2/RXD0/SCL0
35 P6_1/CLK0
36 P6_0/*CTS0/*RTS0
37 P5_7/*RDY/CLKOUT
38 P5_6/ALE
39 P5_5/*HOLD
40 P5_4/*HLDA
41 P5_3/BCLK
42 P5_2/*RD
43 P5_1/*WRH/*BHE
44 P5_0/*WRL/*WR
45 P4_7/*CS3
46 P4_6/*CS2
47 P4_5/*CS1
48 P4_4/*CS0
49 P4_3/A19
50 P4_2/A18
51 P4_1/A17
52 P4_0/A16
53 P3_7/A15
54 P3_6/A14
55 P3_5/A13
56 P3_4/A12
57 P3_3/A11
58 P3_2/A10
59 P3_1/A9
Signal Name I/O
BE_KEY0
BE_KEY1
DAC_DATA_IN
DAC_CS_IN
DAC_CK_IN
BYTE
CNVSS
CONT1
CONT2
RESET
XOUT
GND
XIN
+3.3V_D
NMI
BE_DAC_CS (MLEN1)
DIR1_CFLUG
P_DOWN
BE_FL_CS
CONT3
LED-ON
LED-STBY
DF_RST(BE_DAC_RESET)
MODE2
VOLTAGE-PROTECT
BE_FL_CK
BE_FL_DT
USB-SENS
BE_UART_MOSI
BE_UART_MISO
FS0
28 TXD
28 RXD
BE_DAC_CK
INT 0
BE_DAC_DT
DIR1_AUDIO
EPM
E2P_CLK
E2P_DO
E2P_DI
E2P_CS
CE
USB_RST
LED_AL32
PWB CHECK
PWB CHECK
PWB CHECK
PWB CHECK
DIR1_ERROR
DAC_CONT_SEL
DAC_RST_IN
FL_RST
REMOCON_OUT
BE_RST
MODEL_ID2
DV_STB
DIR1_RST
60
Initial
I H B/E Button Signal 1 D/A Enable PU, PD is impossible
I H B/E Button Signal 2 D/A Enable PU, PD is impossible
O L DAC CONTROL DATA INPUT PORT
O H DAC CHIP SELECT PORT
O L DAC CONTROL CLOCK PORT
I GND
I UP DATE Control terminal
I L [Reserve]
I L [Reserve]
I Reset input
O Main clock output
I Main clock output
I [non] PU to 3.3V_D (R527 : 10k)
I B/E DAC data reception start (end) confirmation port
I DIR data change detection port
I H It is power failure detection and Mute effective.
I B/E FL data reception end confirmation port [outside
interruption]
I L [Reserve]
O Power indicator "ON" control
O Power indicator "OFF" control
I B/E DAC RESET port
I [Reserve] LED AL32 or MP3 44.1k/48k "L" 32k"H"
I H High VOLTAGE-Detect (JP only)
I B/E FL Data Serial Data Clock
I B/E FL Data Serial Data Input
I L [Reserve]
O For B/E UART Rx Data
I For B/E UART Rx Data
O L FS0/FS1 in combination, EXT IN FS type of signal output.
It uses it for the de-emphasis characteristic selection of
O L
FPGA.
O L For USB UART DATA
I For USB UART DATA
I B/E DAC Data Serial Data Clock
O L [Reserve]
I L B/E DAC Data Serial Data Input
I AUDIO/non-AUDIO distinction
O L UP DATE Control terminal
O L EEPROM CLK / UP DATE Control terminal
I EEPROM reading data / UP DATE Control terminal
O L EEPROM writing data / UP DATE Control terminal
O L EEPROM CE / UP DATE Control terminal
O L UP DATE Control terminal
O L USB RESET contlrol
O L AL32 LED control
I PWB board check mode switch 3 , PU R550 : 10k
I PWB board check mode switch 2 , PU R549 : 10k
I PWB board check mode switch 1 , PU R548 : 10k
I PWB board check mode switch 0 , PU R547 : 10k
I DIR1 ERROR distinction
O L Whether SYSCON controls DAC or DV3.2 controls is
switched
O L DAC RESET
O L FL Driver Reset
O L B/E Remocon Code output
O L B/E Reset Signal
I [Reserve]
I B/E start-up confirmation port
O L DIR1 RESET
Function