Analog Devices DC1840C Demo Manual page 8

DEMO MANUAL DC1840C
DEMONSTRATION CIRCUIT 1682B OPERATION
AUTO and MID Jumpers
The AUTO and MID pins of the LTC4271 are set by
jumpers JP1 and JP2 respectively on the DC1682B
(Figure 10). Setting JP1 to HI enables the AUTO pin mode
in the LTC4270/LTC4271 chipset. J2 provides test points
for access to AUTO and MID.
In AUTO pin mode (JP1 high), the LTC4270/LTC4271
2
chipset internal I C registers default to the AUTO pin high
state after a software or hardware reset, or system power
on. The LTC4270/LTC4271 chipset autonomously detects,
powers on and disconnects power to PDs without the
2
need for I C host control.
Setting JP1 to LO disables AUTO pin mode and sets the
LTC4270/LTC4271 chipset to a low current shutdown
2
mode. An I C host controller can then be used to con-
figure the LTC4270/LTC4271 chipset to semi-auto mode
for controlled PSE operation or to manual mode for test
purposes.
Setting JP2 to HI enables the midspan mode detection
backoff timer in the LTC4270/LTC4271 chipset. For end-
point PSEs, set JP2 to LO to disable midspan mode.
For quick PSE evaluation in AUTO pin mode with
MIDSPAN disabled, set JP1 HI and JP2 LO on the DC1682B.
R35
10
C19
D1
1µF
SMAJ58A
100V
C26
0.1µF
V
EE
8
AGND
LTC4270
V
VSSK SENSEn GATEn
EE
D26
RSENSEn
B1100
Qn
FDMC3612
4 × 1.00
Figure 11. DC1682B, 1 of 12 Ports Surge Protection
Surge Protection
Ethernet ports can be subject to significant cable surge
events. To keep PoE voltages below a safe level and protect
the application against damage, protection components,
as shown in Figure 11, are required at the main supply,
at the LTC4270 supply pins and at each port.
Bulk transient voltage suppression (TVS
capacitance (C ) are required across the main PoE
BULK
supply and should be sized to accommodate system level
surge requirements.
Each LTC4270 requires a 10Ω, 0805 resistor (R1) in series
from supply AGND to the LTC4270 AGND pin. Across the
LTC4270 AGND pin and V
TVS (D1) and a 1μF , 100V bypass capacitor (C19). These
components must be placed close to the LTC4270 pins.
Finally, each port requires a pair of S1B clamp diodes:
one from OUTn to supply AGND and one from OUTn to
supply V . The diodes at the ports steer harmful surges
EE
into the supply rails where they are absorbed by the surge
suppressors and the V
of these paths must be low impedance. These S1B diodes
are placed on the DC1680 mother board of the DC1840 kit.
34-PIN
CONNECTOR
DC1682B SIDE
OUTn
Cn
0.22µF
X7R
100V
OUTn
V
EE
DC1840c F11
BULK
pin are an SMAJ58A, 58V
EE
bypass capacitance. The layout
EE
DC1680 SIDE
S1B
PROTECTION
S1B
+
OUTn
C
BULK
TO
PORT
S1B
) and bulk
TVS
BULK
V
EE
Rev E