Mitsubishi Electric RD62P2E Application User's Manual page 67

CH1 Cycle pulse count current value
• The cycle pulse count current value is stored in this area during the execution of the cycle pulse counter function.
• The range of the stored value is between -2147483648 and 2147483647 (32-bit signed binary value).
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory address name
CH Cycle pulse count current value
Although the storage addresses differ between the latch count value and cycle pulse count current value, the
stored values are always the same (updated simultaneously). Therefore, when the latch counter function or
cycle pulse counter function is executed, the latch count value and cycle pulse count current value do not hold
their previous values.
CH1 Ring counter lower limit value setting
• When the counter type is set to ring counter, the lower limit value of the count range is stored in this area.
• The setting range is between -2147483648 and 2147483647 (32-bit signed binary value).
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory address name
CH Ring counter lower limit value setting
CH1 Ring counter upper limit value setting
• When the counter type is set to ring counter, the upper limit value of the count range is stored in this area.
• The setting range is between -2147483648 and 2147483647 (32-bit signed binary value).
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory address name
CH Ring counter upper limit value setting
CH1 Cycle pulse count difference value
• The difference value between the cycle pulse count previous value and cycle pulse count current value is stored in this area
during the execution of the cycle pulse counter function.
• The range of the stored value is between -8589934592 and 8589934591 (64-bit signed binary value).
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory address name
CH Cycle pulse count difference value
CH1
18 to 19
CH1
20 to 21
CH1
22 to 23
CH1
24 to 27
CH2
50 to 51
CH2
52 to 53
CH2
54 to 55
CH2
56 to 59
APPENDICES
Appendix 3 Buffer Memory Areas
A
65