Event Register Sets - Keithley S46 Instruction Manual

S46/S46T/S46L Microwave Switch System Instruction Manual
Figure 3-10
Status model structure
Operation Complete
Query Error
Device Specific Error
Execution Error
Command Error
Power On
(Always Zero)

Event register sets

An event register set is made up of an event register and an event enable register
When an event occurs, the appropriate event register bit sets to 1. The bit remains latched (to 1)
until the register is reset. When an event register bit is set and its corresponding enable bit is set
(as programmed by the user), the output (summary) of the register will set to 1, which in turn sets
the summary bit of the Status Byte Register.
Document number: S46-901-01 Rev. F / March 2011
Output Queue
Standard Event Registers
Event Enable
Event
Register Register
&
OPC OPC
1
1
&
QYE QYE
&
DDE & DDE
EXE & EXE
CME CME
&
6
6
&
PON
& PON
8
& 8
9 9
&
10 10
&
11 11
&
12 & 12
13 13
&
14 14
&
15 & 15
*ESE <NRf>
*ESR?
*ESE?
Error Queue
Status Byte
Register
0
1
EAV
3
MAV
ESB
RQS/MSS
7
*STB?
Logical Master Summary Status (MSS)
OR
EAV = Error Available
MAV = Message Available
ESB = Event Summary Bit
RQS/MSS = Request for Service/Master
Note: RQS bit is in serial poll byte,
MSS bit is in *STB? response.
Section 3: Operation
Service Request
Enable Register
& 0
1
&
EAV
&
Logical
3
&
OR
& MAV
ESB
&
6
7
&
*SRE
*SRE?
Summary Status
(Figure 3-11).
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