Fluke 9100 Series Service Manual page 31

Table 2-6.
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ADDRESS WRITE
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$DOX01 COMMAND0-
$DOX11 COMMAND1-
$DOX21 Drive Register 2 (U25)
$DOX31 Loop Counter Load
(LCLO- or LCHI-)
$DOX41 RAM-PORT-
$D0X51 RAM-STROBE
$DOX61 LOAD-RAM-HI-
$DOX71 LOAD-RAM-LO-
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Performing a write to $DOX11 toggles the COMMAND1- output of U10 (Top
PCA), thereby latching the data on the bus into the U6 register.
Performing a read at this address has no effect. See the Table 2-9 for
more information.
Performing a write to $DOX21 selects U25 (Main PCA) by address decoding
and latches the data on the bus into Drive Register 2 on U25. Performing
a read at this address has no effect. See the headings, "Internal
Oscillator Control Functional Block", the "Loop Control Functional
Block", and Table 2-7 for more information.
Performing a write to $DOX31 toggles either LCLO- or LCHI- of U25 (Main
PCA), depending on the state of bit 3 of Drive Register 2 on U25,
thereby loading the least significant byte (LSB) or most significant
byte (MSB) of the loop count into U26 or U27. Performing a read at this
address has no effect. See the heading, "Loop Control Functional Block",
and Table 2-7 for more information.
Performing a read or a write to $DOX41 toggles the RAM-PORT- output of
U10 (Top PCA), thereby incrementing the chip counter U9 and updating
which SRAM is selected by U11. The actual data returned by a read is
disregarded.
Performing a write to $DOX51 toggles the RAM-STROBE output of U10 (Top
PCA). This output can be used as a software-controlled clock for driving
vectors. Performing a read at this address has no effect.
Performing a write to $DOX61 toggles the LOAD-RAM-HI- output of U10 (Top
PCA), thereby latching the data on the bus into the upper byte register
U3 of the Loop-Back Address. Performing a read at this address has no
effect.
Performing a write to $DOX71 toggles the LOAD-RAM-LO- output of U10 (Top
PCA), thereby latching the data on the bus into the lower byte register
U4 of the Loop-Back Address. Performing a read at this address has no
effect.
Vector I/O Module Output Section Address Map
2-19
2/Theory of Operation
READ
Vector Drive Status Nybble
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RAM-PORT-
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