Fluke 9100 Series Service Manual page 10

Vector output i/o module
Hide thumbs Also See for 9100 Series:
Table of Contents

Advertisement

1/Introduction and Specifications
Table 1-1. Vector Output I/O Module Specifications (cont.)
______________________________________________________________________________
WAIT (Handshake) Setup Time (twsu) ......... 42.5 ns maximum (35 ns typical)
Single Module Channel to Channel Skew* ..... 6 ns maximum (1 ns typical).
Module to Module Channel Skew* ............. 10 ns maximum (1 ns typical).
TRISTATE-:
Activation (txout) ..................... Output source/sink released 25
Recovery (txsu) ........................ TRISTATE- must go high no later
Output Series Termination .................. 33 Ohms
Capture Clock:**
INT CLK ................................ Capture Clock clocks 42.5 ns
DR CLK ................................. Capture Clock clocks 55 ns
START, STOP, and ENABLE:
START, STOP Pulse Width .................... 10 ns minimum.
INT CLK
START Setup Time .................. 30 ns minimum.
STOP Setup Time ................... 30 ns minimum.
ENABLE Setup Time ................. 25 ns minimum.
ENABLE Hold Time .................. 20 ns minimum.
______________________________________________________________________________
*
Skew measurement assumes equal loading. Differences in capacitance
may affect results.
**
Capture clock may be adjusted in approximate 15 ns steps by using the
setoffset command (see the 9100 Series TL/1 Reference Manual).
______________________________________________________________________________
from WAIT acknowledgement until
next clock cycle drives vector.
If the setup time is not met,
the next clock drives out the
vector. Minimum WAIT pulse
width is 10 ns.
ns maximum (20 ns typical)
after TRISTATE- goes low.
Minimum TRISTATE- pulse width
is 10 ns.
than 5 ns after the rising edge
of the INT CLK or no later than
10 ns after the programmed edge
of DR CLK for the vector to be
output by that clock, otherwise
that vector is only driven
internally and the output is
held tri-stated, effectively
skipping that vector.
±5 ns after the falling edge
of INT CLK.
±10 ns after non-clocking edge
of DR CLK (approximate 50% duty
cycle).
1-2

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

9100a-017

Table of Contents