Yaesu FT-8100R Technical Supplement page 24

- - - - - - - - - - - - - - Circuit Description
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Unit. Th is con tro l data is se nt to sh ift register
Q2039
( ~ P D40 94 B G),
from w hich a voltage ap-
prop r iate to the control data va lue is se n t to
Q2022 as a reference vo ltage.
Q2022 (FMS 1) diffe re ntia lly-amp lifies the rec-
tified DC vo ltage from th e power m odule and
the reference vo ltag e from t he s hift register.
Q202 1 (IMX1)
co
nverts th is di fference in to the
control voltage for Q2022.
A Pe
cont roller Q2024
(2S A1870E) outputs an appropriate control volt-
age a nd varies the APC voltage at p in 2 o f the
powe r modu le and ·n O-d r ive circuit, the reby
controlling the RF o utput level. It is po ssible to
select " Hig h", " Mid", or "Low" for the RF ou t-
pu t power levels.
If the PLL circu it unlocks d uring tran s mission,
p in 2 of Q2032 (SC370651F) turns " High" and
an un lock signal is sent from Q2036 (DTA143EK).
This unlock sig nal is input to Q202 1 (IMX1) to
di sable Q20 21 (IMX1). At the same time, Arc
controller Q2024 (2S A1870 E) voltage to become
o
V, thus d isabling transmission from the po wer
mod ule and 430-drivl' circu it. During rec ep tion,
a voltage simi lar to an u n lock signa l is sent to
Q2021 (IMX1), and the APe voltages of the pow-
er modu le and 430-drive circu it beco me 0 V,
transmi ssion is disabled .
VHFPLL
The PLL circu it consists of PLL subsystem IC
Q1033 (S C370651F), w h ich includ es a compa r-
ative frequ en cy d ivide r, referen ce frequen cy d i-
vider, phase compa rator, charge pump, shift reg-
ister, latch, etc.
The output from pin 2 of J4301 of the 144.vCO
Un it is divid ed by th e com pa ra tive frequen cy
divider accord ing to the frequ en cy di viding d ata
that is associated w ith the setting frequen cy in-
p u t from the CPU . It is then sen t to th e phase
IT-BlOOR Tf'clrnical Supplement
comparator.
The 12.8 MHz freque ncy of the reference os-
cillator circ u it ma de up of XI002 and Q 1029
(2S C2812-L6) is di vid ed by th e reference fre-
q uen cy d ivid er in to 2,560 o r 2,048 parts to be-
come 5 kHz or 6.25 kH z comparative referen ce
freque ncies, which are utilized by the phase com-
parator. Eithe r of the comparative reference fre-
quencies is selected according to freq uency steps:
5 kHz is selected for the 5/ 10/15 /20 kH z steps,
and 6.25 kHz Is selected for the 12.5/ 25/ 50 kH z
steps.
The p hase compa rator co mpa res the p hase
between the freq uency-divided osc illation fre-
quency of the VCO circuit and comparative ref-
ere nce freq uen cy (5 kHz or 6.25 kH z ) a nd its
ou tput is a p ulse correspond ing to the phase dif -
feren ce. This pulse is integrated by the charge
pump and loo p filter into a control voltage (VCV)
to control the osci llatio n freq ue ncy of the VCO
circu it.
W hen the power is tu rn ed on or the tx /rx
operation is switched, the freq ue ncy and the fre-
qu en cy di vid ing ratio d ata for the reference fre-
qu ency d ivider are seria lly tra nsmitted from the
CPU to the d ivider. This seria l d ata is conve rted
by the shift register a nd latch into pa ra llel da ta
to cont ro l th e reference frequen cy divid er and
compa rative freq ue ncy divider.
Th e p resence or absence of p hase d ifferen ce
as t he result of co mpa rison by the phase co m-
par ator is sent as a n "Un lo c k" signa l from the
lock detector circu it insid e the PLL Ie. Thi s sig-
nal is sent to the APe circuit to disable transmi s-
sion w hen the PLL circu it is u nlocked .
UHF PLL
The PlL circu it consists o f PLL s ubsystem IC
Q2032 (SC370651F), w hich includes a compa r-
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