Samsung SF-530 Service Manual page 96

CIRCUIT DESCRIPTION
Signal
nECS[1:0]
nRCS[2]
nRCS[1]/GOPA[7]
nRCS[0]
SC_CONPHA/
GOPA[19]
SC_CONPHB/
GOPA[20]
SC_CUR[3:0]
PWMO[2:0]/
GOPA[13:11]
VDO2/GOPA[29]
VDO1/GOPA[14]
LSU_CLK/
GOPA[15]
nHSYNC1/GIP[10]
nLREADY/GIP[11]
nHSYNC2/GIP[12]
VDI/GIP[13]
VCLK/GIP[14]
nEXTWAIT/GIP[7]
RTCXIN
RTCXOUT
SLED[2:0]/
GOPA[18:16]
GAVRT
GAIN[2:0]
RTC_VDD
Signal
VDD_PLL
SAVDD
SAVSS
GAVSS
3VDD
5VDD
VSS
Repair Manual
3-6
Pin No. I/O Type
Not external chip select. Three I/O banks are provided for
external memory-mapped I/O operations. Each I/O bank
12,13 O1
contains up to 4M half-word. The nECS signals indicate that
an external I/O bank is selected.
51 O2
50 O1
corresponds to ROM/SRAM bank 0, nRCS[1] to bank 1, and
49 O1
102 O1 Scan motor control/Bi-phase
105 O1 Scan motor control/Bi-phase
103, 104,
O1 Scan motor bi-current/uni-phase
106, 107
118~120 O1 PWM out signal
121 O4 Video out from PIFC
122 O5 Video out from LSU control
123 O1 Clock for LSU motor
125 I1 HSYNC1
126 I1 LSU ready
127 I1 HSYNC2
128 I2 Video data input from RET
129 I2 External video clock
130 I3 External wait
202 I7 RTC oscillator clock input.
203 O7 RTC oscillator clock output.
196~198 O1 CIS LED signals
205 I5 Top reference voltage for general ADC
206~208 I5 Analog inputs for general ADC
201 RTC VDD.
Pin No. I/O Type
186
1
5
204
15, 30, 81,
115, 131,
160
48, 67, 89,
141, 195
11, 25, 39,
58, 76, 101,
108, 124,
150, 172,
181
Description
Not ROM/SRAM chip select. The KS32C65100 can access
up to three external ROM/SRAM banks. nRCS[0]
nRCS[2] to bank 2. By controlling the nRCS signals, CPU
addresses can be mapped into the physical memory banks.
PLL power (3.3V).
Analog power for scan ADC and general ADC (3.3V).
Scan ADC ground.
General ADC ground
3.3V internal power.
Externally connected to the 3.3V regulator.
5V I/O power.
Externally connected to the VCC board plane.
System ground.
Externally connected to the ground board plane.
Description
Samsung Electronics