COBHAM GR712RC Quick Start Manual
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COBHAM GR712RC Quick Start Manual

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GR712RC
Dual-Core LEON3FT SPARC V8 Processor.
2018 User's Manual
The most important thing we build is trust
Quick Start Guide for GR712RC-BOARD
GR712RC-QSG
November 2018, Version 1.0
1
www.cobham.com/gaisler

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Summary of Contents for COBHAM GR712RC

  • Page 1 GR712RC Dual-Core LEON3FT SPARC V8 Processor. 2018 User's Manual The most important thing we build is trust Quick Start Guide for GR712RC-BOARD GR712RC-QSG www.cobham.com/gaisler November 2018, Version 1.0...

  • Page 2: Table Of Contents

    5.9. GRMON Debug Link Limitations ..................22 5.10. MIL-1553 ........................22 5.11. CAN multiplexing ....................... 22 5.12. Concurrent CAN and Ethernet ..................22 5.13. Hardware behavior at CPU reset and power management ........... 23 6. Support ..........................24 GR712RC-QSG www.cobham.com/gaisler November 2018, Version 1.0...

  • Page 3: Introduction

    The purpose of this document is to get users quickly started using the board. For a complete description of the board please refer to the GR712RC Development Board User Manual. The GR712RC system-on-chip is described in the GR712RC User Manual.

  • Page 4: Board Configuration

    2. Board Configuration 2.1. Overview The primary source of information for board configuration is the GR712RC Development Board User Manual. The board requires some hardware configuration to fit with the customer requirements. In particular, the number of the GR712RC-BOARD's processor I/O pins limits the simultaneously available connections to external interfaces.

  • Page 5: I/O Switch Matrix

    Six basic example configurations are provided to respond to typical use cases, as seen in Table 2.1. To use one of these configurations, the user has to insert jumpers JP3 through JP66 in the position described in the table. Refer to [RD-1] and GR712RC Development Board Schematic for more information on signal and GPIO configuration. Table 2.1. Typical configurations Jumper Cfg.

  • Page 6: Uart

    UART1 Rx is multiplexed and JP3 must be set to 3-4 in order to use it. Refer to the GR712RC Development Board Schematic for more information on how to configure UART0 and UART1 to use the RS422 standard.

  • Page 7: Grmon Hardware Debugger

    The first step is to set up a debug link in order to connect to the board. The following section outlines which debug interfaces are available and how to use them on the GR712RC Development Board, after that a basic first inspection of the board is exemplified.

  • Page 8: Connecting To The Board

    • The GR712RC has a clock-gating unit which is able to disable/enable clocking and control reset signals. Clocks must be enabled for all cores that LEON software or GRMON will be using. The grcg command is described in [RD-4]. 3.4. Connecting to the board In the following example the FTDI debug-link is used to connect to the board.
  • Page 9 AHB: 80100000 - 80200000 occan0 Aeroflex Gaisler OC CAN AHB interface AHB: FFF30000 - FFF31000 IRQ: 5 cores: 2 ahbram0 Aeroflex Gaisler Generic FT AHB SRAM module AHB: A0000000 - A0100000 APB: 80100000 - 80100100 GR712RC-QSG www.cobham.com/gaisler November 2018, Version 1.0...
  • Page 10 0x80100808 Node address 0x000000fe 0x8010080c Clock divisor 0x00000000 0x80100810 Destination key 0x00000000 0x80100814 Time 0x00000000 0x80100818 Timer and Disconnect 0x00000000 0x80100820 DMA Channel 0 control/status 0x00000000 0x80100824 DMA Channel 0 rx maximum length 0x00431000 GR712RC-QSG www.cobham.com/gaisler November 2018, Version 1.0...
  • Page 11 Address Space Register 0x00000000 0xfff1002c Receive Read Pointer Register 0x00000000 0xfff10030 Receive Write Pointer Register 0x00000000 CCSDS Telemetry Encoder 0x80000b00 DMA control register 0x00000004 0x80000b04 DMA status register 0x00000000 0x80000b08 DMA length register 0x00400002 GR712RC-QSG www.cobham.com/gaisler November 2018, Version 1.0...
  • Page 12 Command register 0x00000000 0x80000430 Transmit register 0x00000000 0x80000434 Receive register 0x20880021 General Purpose Register 0x80000600 GR712RC general purpose register 0x00000000 General Purpose I/O port 0x80000900 I/O port data register 0x419ff955 0x80000904 I/O port output register 0x00000000 0x80000908 I/O port direction register...
  • Page 13 16-bit scalar, 4 * 32-bit timers, divisor 80 The GR712RC has a clock-gating unit which can disable and enable clock gating and generate reset signals of certain cores in the SOC. With the GRMON grcg command the current setting of the clock-gating unit can be inspected and changed, the command line switch -cginit also affects the clock-gating unit.
  • Page 14 GRCLKGATE GR712RC info: Unlock register: 0x00000000 Clock enable register: 0x00000007 Reset register: 0x00000ff8 GR712RC decode of values: +------+----------+----------------------------+----------+---------+-------+ | Gate | Core(s) | Description | Unlocked | Enabled | Reset | +------+----------+----------------------------+----------+---------+-------+ | GRETH | 10/100 Ethernet MAC...

  • Page 15: Software

    C and C++ applications for LEON2, LEON3 and LEON4. This section gives the reader a brief introduction on how to use BCC together with the GR712RC Development Board. It will be demonstrated how to install BCC, build an existing sample project and run it on the board using GRMON.

  • Page 16: Running And Debugging With Grmon

    4.2.3. Running and debugging with GRMON Once your application is compiled, connect to your GR712RC-BOARD with GRMON. The following log shows how to load and run an application. Note that the console output is redirected to GRMON by the use of the -u command line switch, so that the application standard output is forwarded to the GRMON console.

  • Page 17: Rtems Real Time Operating System

    4.3. RTEMS Real Time Operating System 4.3.1. Overview RTEMS is a real time operating system maintained at [RD-5] that supports the LEON CPU family. Cobham Gaisler distributes a precompiled RTEMS toolchain for LEON called RCC [RD-6]. This section gives the reader a brief introduction on how to use RTEMS together with the GR712RC Development Board.

  • Page 18: Running And Debugging With Grmon

    4.3.4. Running and debugging with GRMON Once your executable is compiled, connect to your GR712RC-BOARD with GRMON. The following log shows how to load and run an executable. Note that the console output is redirected to GRMON by the use of the -u command line switch, so that printf output is shown directly in the GRMON console.

  • Page 19: Mkprom2

    PATH, together with a valid SPARC toolchain ( sparc-gaisler-elf, sparc-elf, sparc- rtems or sparc-linux). To generate a boot PROM for a GR712RC Development Board and running your program from SRAM: mkprom2 -leon3 -freq 80 -rmw -ramsize 8192 -romsize 8192 -baud 38400 -ramws 2 -o hello.prom hello.exe This example command will work for a board in the default configuration at delivery, with a system clock fre- quency of 80 MHz.

  • Page 20: Vxworks

    4.5. VxWorks 4.5.1. Overview VxWorks is an embedded real-time operating system developed by WindRiver. Cobham Gaisler provides a LEON architectural port (HAL) and a Board Support Package (BSP) in full source code for VxWorks. The VxWorks package includes a quick start guide and technical support. Contact support@gaisler.com for more information.

  • Page 21: Frequently Asked Questions / Common Mistakes / Know Issues

    5.7. Multiprocessor & legacy support Code compiled for the single core LEON3 will generally be able to run unmodified on the GR712RC. The second core is inactivated after reset and unless it's activated (by writing a specific bit in the IRQ controller) it will remain inactivated and the chip will behave as a single-CPU system.

  • Page 22: Interrupts

    The correct RTEMS driver to use for the MIL-1553 core is B1553BRM. This should not be confused with GR1553B which is the driver for Cobham Gaisler's in-house developed core. To use the core, users need to set up clock gating and clock selection with the general purpose register.

  • Page 23: Hardware Behavior At Cpu Reset And Power Management

    "proprietary" interface is obsolete and not part of the public interface of the GR712RC but are still part of the I/O switch matrix. When the CAN interface is enabled, the pins 191, 190, 185, 184 and 172 are also driven with "random values"...

  • Page 24: Support

    6. Support For support contact the Cobham Gaisler support team at support@gaisler.com. When contacting support, please identify yourself in full, including company affiliation and site name and address. Please identify exactly what product that is used, specifying if it is an IP core (with full name of the library distribution archive file), component, software version, compiler version, operating system version, debug tool version, simulator tool version, board version, etc.
  • Page 25 Cobham convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Cobham or of third parties. All information is provided as is. There is no warranty that it is correct or suitable for any purpose, neither implicit nor explicit.

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