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Summary of Contents for COBHAM GR-CPCI-GR740
- Page 1 GR-CPCI-GR740 Development Board 2017 User's Manual The most important thing we build is trust GR-CPCI-GR740 Development Board User's Manual GR-CPCI-GR740-UM, 2017, Version 1.7 www.cobham.com/gaisler...
- Page 2 GR-CPCI-GR740 Intentionally Blank GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler...
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Page 3: Table Of Contents
33 / 66 MHz PCI Bus Speed................35 Ethernet Interface....................36 FPGA for PCI Arbiter & Versaclock Controller..........38 Spacewire (LVDS) Interfaces................39 4.9.1 SPW interface circuit..................39 4.9.2 SPW Connectors....................39 4.10 FTDI Serial to USB Interface................40 4.11 SPI interface...................... 47 4.12 GPIO........................48 GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... - Page 4 4.16.4 Watchdog......................62 4.16.5 JTAG interface....................62 4.17 Heatsink/Fan......................63 Setting Up and Using the Board................... 64 Interfaces and Configuration..................67 List of Connectors..................... 67 List of Oscillators, Switches and LED's............79 List of Jumpers....................81 Change Record.......................86 GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler...
- Page 5 Figure 4-2: GR740 Package ......................12 Figure 4-3: GR-CPCI-GR740 Board Block Diagram................ 13 Figure 4-4: GR-CPCI-GR740 Board with CPCI Front Panel ............14 Figure 4-5: Example of GR style 6U board Mounted in Enclosure..........15 Figure 4-6: GR-CPCI-GR740 board Front Panel Concept..............15 Figure 4-7: Auxiliary PCB for DIP Switches and front panel GPIO connections......16...
- Page 6 Table 27: List and definition of Oscillators and Crystals..............71 Table 28: List and definition of PCB mounted LED's................71 Table 29: List and definition of Switches................... 71 Table 30: DIP Switch FP-S3 definition....................72 Table 31: List and definition of PCB Jumpers................... 73 GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler...
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Page 7: Introduction
GR-CPCI-GR740 Introduction Scope of the Document This document establishes the User's Manual for the activity “GR-CPCI-GR740” initiated by the European Space Agency under ESTEC contract N/A. The work has been performed by Cobham Gaisler AB, Göteborg, Sweden. Reference Documents [RD1] "Quad Core LEON4 SPARC V8 Processor, GR740, Data Sheet and User's... -
Page 8: Abbreviations
Gigibit Media Independent Interface GPIO General Purpose Input / Output Input/Output Intellectual Property Logic Analyser Media Independent Interface Multiplexer Printed Circuit Board System On a Chip Spacewire To Be Confirmed To be Confirmed To Be Defined GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 9: Introduction
Overview This document describes the GR-CPCI-GR740 Development Board. This equipment is intended to be used for the functional validation of the Cobham Gaisler GR740 Processor. Furthermore, this board provides developers with a convenient hardware platform for the evaluation and development of software for the GR740 processor. - Page 10 • Push Button switch for RESET and toggle switch (on/off) for BREAK • LED indicators for POWER, ERRORN, DSU Active and GPIO • Assorted jumpers and Test Points for configuration and Test of the board GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler...
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Page 11: Handling
This board is intended for commercial use and evaluation in a standard laboratory environment, nominally, 20°C. All devices are standard commercial types, intended for use over the standard commercial operating temperature range (0 to 70ºC). GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 12: Board Design
Board Design GR740 Processor The Cobham Gaisler GR740 processor is a radiation-hard system-on-a-chip featuring a quad-core fault-tolerant LEON4 SPARC V8 processor, and a set of IP cores connected through AMBA AHB/APB buses as represented in the figure below and as specified in [RD1]. -
Page 13: Board Block Diagram
2 x CAN 2 x CAN PB SWTICH Figure 4-3: GR-CPCI-GR740 Board Block Diagram Note that not all features and interface are available at the same time, and the configuration of jumpers and connectors plus some programming of registers is required to access some of the features. -
Page 14: Board Mechanical Configuration
Compact PCI rack, this board is provided with a custom CPCI front panel with the appropriate connector cut-outs. The board in the standard configuration with the with CPCI front panel mounted is shown in Figure 4-4. Figure 4-4: GR-CPCI-GR740 Board with CPCI Front Panel GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 15: Front Panel
As an alternative to the Compact PCI 6U format of the board, this concept allows the same PCB design to be installed in a Elma Type 33 style to allow convenient bench-top use of the Unit, in a similar manner to other Cobham Gaisler development boards (e.g. as shown Figure 4-5). -
Page 16: Figure 4-7: Auxiliary Pcb For Dip Switches And Front Panel Gpio Connections
In the enclosure version of the board, since there is not enough front-panel height available to fit these connectors, this PCB will have to be mounted at the back of the enclosure, and the ribbon cable appropriately adapted. GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 17: Memory
64 Mbit of flash PROM, in Parallel 8/16 bit flash device 4.5.1 SDRAM Memory Interface configuration The GR-CPCI-GR740 board provides a 96 bit wide SDRAM data interface using two SODIMM modules. However, the GR740 processor has various memory operation modes which includes... -
Page 18: Sdram Sodimm 48/96 Bit Interface
Due to the size and configuration of the SODIMM sockets, one socket is mounted on the top side and the other socket on the bottom side of the board, in a 'mirror image' as represented in the figure below. GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 19: Promio / Interface Configuration
YOU MUST NOT TRY TO USE FORCE TO REMOVE THE CARD! Instead the adjacent card will have to be loosened or removed first in order to allow the GR-CPCI-GR740 card to be removed. SDRAM Clock Phase Adjustment A clock phase shifter circuit is defined to enable an adjustable phase shift of the SD_CLK phase relation between ASIC and SODIMM module to be performed. -
Page 20: Promio / Parallel Flash
This device (Intel/Numonyx/Micron JS28F640J3 Strataflash) provides 64Mbit of Non- Volatile storage, organised as 8M x 8 bits (4M x 16 bits), operating with an I/O voltage of in the range of 2.7V to +3.3V. GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 21: Memory Expansion
Memory Expansion The GR740 processor does not support the addition of SRAM memory. However, the following memory bus signals are connected to a 120 pin AMP connector (AMP 5-177984-5), J9: DATA[15..0] ADDR[27..0] WRITEN READ IOSN GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 22: Figure 4-10: Mezzanine Connector Pin Number Ordering
The reason for this is explained in more detail in the Technical Note, [RD5]. Therefore please take care when designing your own mezzanine boards to take account of this pin ordering. Figure 4-10: Mezzanine Connector Pin Number Ordering GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 23: Pci Interface
1. GR740 as Host connected to primary side of PCI-PCI Bridge and from there to Backplane 2. GR740 as Peripheral to secondary side of PCI-PCI Bridge and from there to Backplane 3. GR740 as Host connected directly to Backplane 4. GR740 as Peripheral connected directly to Backplane GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 24: Figure 4-11: Pci Interface Configurations
'keyed', although there is a visual hint whereby the pin 1 of the connectors is marked by the diagonal corner. Ensure that the PCI-PCI Mezzanine is fitted as shown in Figure 4-14. GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 25: Figure 4-12: Pci Peripheral-Host-Bridge Connections
GR740 GR740 GR740 PCI-X PCI-X PCI-X PCI-X PCI-P PCI-P PCI-P PCI-P PRIMARY PRIMARY PCI-PCI PCI-PCI BACKPLANE BACKPLANE BACKPLANE BACKPLANE Bridge Bridge Figure 4-12: PCI Peripheral-Host-Bridge Connections Figure 4-13: Connectors for mounting PCI-PCI Configuration Mezzanine GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 26: Pci Data/Address/Control Bus
4. PCI IDSEL, Reset configuration 4.6.1 PCI data/address/control bus The signals comprise the data, address and control signals for a 32 bit PCI interface: PCI_AD[31..0] PCI_CBE[3..0] PCI_CLK PCI_DEVSELN PCI_FRAMEN PCI_GNT PCI_IDSEL PCI_IRDYN PCI_PAR PCI_PERRN PCI_REQ GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 27: Pci Clock Distribution
33/66MHz clocks to the GR740 and to the secondary side clock of the PCI-PCI Bridge. Additionally, a clock is required for the secondary side arbiter. 3. With the GR740 as Host connected directly to Backplane, a 33/66 MHz GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... - Page 28 Z, by removing the clock oscillator input to the CY2305. This is necessary in the case that the GR740 is operating as a peripheral with no bridge since the peripheral board should not drive the clocks of the other slots. A jumper JP22 is provided to achieve this. GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler...
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Page 29: Figure 4-15: Pci Clock Distribution
OSC. OSC. buffer buffer GR740 PERIPHERAL, NO BRIDGE PCI-MEZZ-4 GR740 GR740 PCI-PCI Bridge BACKPLANE BACKPLANE ARBITER ARBITER FPGA FPGA Zero Zero 33MHz 33MHz delay delay OSC. OSC. buffer buffer Figure 4-15: PCI Clock Distribution GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 30: Arbiter Signal Distribution
2-Master Arbiter 8 Master Arbiter GNT/REQ9 & GNT/REQ10 GNT/REQ[6..1] & GNT/REQ[7..8] GNT/REQ8 & GNT/REQ10 not used not used GNT/REQ[6..1] & GNT/REQ[7] & [10] not used not used Table 2: PCI Arbiter connections for modes 1-4 GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 31: Figure 4-16: Arbiter Signal Distribution
GR740 HOST, NO BRIDGE PCI-MEZZ-3 GR740 GR740 PCI-PCI Bridge BACKPLANE BACKPLANE ARBITER ARBITER FPGA FPGA GR740 PERIPHERAL, NO BRIDGE PCI-MEZZ-4 GR740 GR740 PCI-PCI Bridge BACKPLANE BACKPLANE ARBITER ARBITER FPGA FPGA Figure 4-16: Arbiter Signal Distribution GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 32: Pci Interrupts & Pci_Hostn
BACKPLANE BACKPLANE BACKPLANE BACKPLANE GR740 GR740 PCI-PCI PCI-PCI GR740 GR740 Bridge GR740 GR740 Bridge GR740 PERIPHERAL, NO BRIDGE GR740 HOST, NO BRIDGE BACKPLANE BACKPLANE BACKPLANE BACKPLANE GR740 GR740 GR740 GR740 Figure 4-17: IDSEL Distribution GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 33: Pci Reset
(X3). To enable either 33 MHz or 66 MHz to be used, this oscillator is socketed and the user can exchange and install the correct oscillator, as appropriate. A backplane pin M66EN pin is connected to the ASIC, and is intended in the PCI GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 34: Ethernet Interface
Ethernet Interface The GR740 processor device incorporates two Ethernet controllers with support for GMII and MII interfaces, and the GR-CPCI-GR740 Development Board has two Micrel KSZ9021GN 10/100/1000Mbit/s Ethernet PHY transceivers. These are connected to a dual RJ45 connector on board (J3). -
Page 35: Figure 4-19: Block Diagram Of Ethernet Gmii/Mii Interface (One Of 2 Interfaces Shown)
5P49V5943 (or a similar one) is implemented. This is a flexible device which is controlled via an I2C interface. The automatic programming of the device requires that an I2C sequencer and parameter storage which is implemented in the on-board FPGA. GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 36: Fpga For Pci Arbiter & Versaclock Controller
'0' => install 60-71 MHz '0' => install '1' => open 70-83 MHz '1' => open '0' => install 83-100 MHz '1' => open '1' => open Table 3: SD-CLK Frequency Range Jumper Settings GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 37: Spacewire (Lvds) Interfaces
SPW_DBG signals are shared with GPIO functions, and are LVCMOS (3.3V logic) and required an LVDS driver and receiver circuit. The PCB traces for the LVDS signals on the GR-CPCI-GR740 board are laid out with 100-Ohm differential impedance design rules and matched trace lengths. -
Page 38: Ftdi Serial To Usb Interface
1. Connect JTAG to FTDI Port-A 2. Use JTAG on 6-pin 0.1” Header 3. Connect Power Measurement I2C interface to FTDI Port-B 4. Connect to Power Measurement I2C on 6-pin 0.1” Header 5. Connect UART0 to FTDI port C GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 39: Spi Interface
10 pin 0.1” header on the board to allow an external circuit SPI circuits to be hooked-up. As an example SPI circuit, the GR-CPCI-GR740 Board provides an AD7814, Temperature monitor circuit on the board, which is selected with the SPI_SLVSEL0 GR-CPCI-GR740-UM, Sep 2017, Version 1.7... -
Page 40: Gpio
GPIO lines are configured as inputs. When programmed as outputs the DIP switches should be left in the 'open' ('float') state. Note that the state of the GPIO pins is sampled at power-up or reset of the processor in GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... - Page 41 GPIO[10] should be consistent with the setting of Jumper JP6 pins 11-12 (installed = 8 bit; uninstalled = 16 bit interface) in order that the board can successfully execute its program from Prom at start up. GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler...
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Page 42: Table 4: Gpio Definitions
Otherwise the PROM/IO interface pins are routed to their alternative functions. See §3.2.1 of [RD4]. This bit does not affect board functionality, the board jumpers also need to be configured appropriately to enable the PROM (Flash) Table 4: GPIO Definitions GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 43: Bootstrap Signals
Due to limited front panel space, some of the 'optional' interfaces are accommodated by a separate accessory board with a separate one-slot front panel. The following features are installed on this accessory board which is connected to the GR-CPCI-GR740 board with an appropriate ribbon cable: • Dual CAN 2.0 Interfaces •... -
Page 44: Can 2.0 Interfaces
Instruments which operate from a single +3.3V power supply. D-sub 9 pin connectors are provided on the front panel. CAN_H CAN_L TRANSCEIVER TRANSCEIVER CAN_H CAN_L TRANSCEIVER TRANSCEIVER Figure 4-26: Block Diagram of the CAN interface GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 45: Configuration Of Bus Termination
Since there are various 'standard' connectors defined for the connection to MIL-STD- 1553 bus, and because of limited PCB and front panel area, it a D-sub 9-Male connector on the front panel to accommodate both the A and B bus connections. A D-sub 9-Male GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 46: Serial Interface (Rs232)
GR740 DRIVER/ RECEIVERS Figure 4-29: Serial interface Note: As explained in section 4.10, the serial interfaces of the GR740 processor can either be connected to these front panel connectors (RS232) or to the FTDI-USB GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 47: Debug Support Unit Interfaces
Program download and debugging to the processor is performed using the GRMON Debug Monitor tool from Cobham Gaisler (RD-5). The GR740 processor provides an interface for Debug and control of the processor by means of a host terminal via its DSU interface, as represented in Figure 4-30. - Page 48 GR-CPCI-GR740 EDCL Ethernet Debug Communication Link (connector J1A (Upper) or J1B (Lower)) GRMON can be used with the above listed interfaces. For more information, please refer to [RD4]. GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler...
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Page 49: Other Auxiliary Interfaces And Circuits
4.16.1 Oscillators and Clock Inputs The oscillator and clock scheme for the GR-CPCI-GR740 Board is shown in Figure 4- The main oscillator providing the SYS_CLK for the GR740 ASIC. To enable different oscillator frequencies to be used, a DIL socket is provided which accepts 4 pin DIL8 style 3.3V oscillator components. -
Page 50: Figure 4-31: Board Level Clock Distribution Scheme
33 or 66 MHz BUFFERS BUFFERS XTAL 25MHz XTAL DIL-8 SOCKET XTAL 25 MHz 25 MHz 7 x PCI_SLOTS Arbiter Arbiter Circuit Circuit MEMORY EXPANSION CONNECTOR MEMORY EXPANSION CONNECTOR Figure 4-31: Board level Clock Distribution Scheme GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 51: Power Supply And Voltage Regulation
All other necessary voltages on the board are derived from this input using discrete Power circuits on the board (DC/DC or Linear Regulators as appropriate). On board regulators generate the following voltages: • +3.3V for the GR-CPCI-GR740 I/O voltage, interfaces and other peripherals • +2.5V for GR740 SPW interface I/O voltage •... - Page 52 Memory Expansion connector, J9, in case this could be useful for supplying circuits on User Defined mezzanine boards mated to J9. Note though, that in the case that the board is not powered via the CPCI backplane, that these pins will be unpowered. GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler...
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Page 53: Figure 4-32: Power Regulation Scheme
10A max ETH-PHY adjust min/nom/max DVDD_PLL 5V from PCI Backplane VIO (3V3) MEZZANINE +/-12V from PCI CONNECTOR Backplane (< 0.5A) Not used on this board 3.3V from PCI Backplane Figure 4-32: Power Regulation Scheme GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 54: Reset Circuit And Button
Connector J11, a 6 pin 0.1” header connector provides the JTAG connection for a Digilent Style JTAG cable, or with flying leads to a Xilinx Style JTAG cable. This interface allows DSU Debug over the JTAG interface to be performed. GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 55: Heatsink/Fan
This header provides +VIN and DGND connections. The selected Fan should be compatible with the input voltage which is being provided to the board (range 5V to 14V). There is no active monitoring and control of the heatsink-fan provided. GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 56: Setting Up And Using The Board
VC1-PROG, do not install for parameters to be loaded via I2C JP22 Install BP-CLK (Host Mode) all clocks present on BP JP23 Install M66EN; Force backplane to 33MHz JP24 Not installed Configuration options for Versaclock PLL ranges Table 6: Default Setting of Jumpers GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 57: Table 7: Default Setting Of Switches
ERROR condition, with the ERROR LED illuminated. To perform program download and software debugging on the hardware it is necessary to use the Cobham Gaisler GRMON2 debugging software, installed on a host PC (as represented in Figure 4-30). Please refer to the GRMON2 documentation for the installation of the software on the host PC (Linux or Windows), and for the installation of the associated hardware dongle. - Page 58 Program download and debugging can be performed in the usual manner with GRMON2. More information on the usage, commands and debugging features of GRMON2, is given in the GRMON2 Users Manuals and associated documentation. GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler...
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Page 59: Interfaces And Configuration
Configuration plug for 96bit SDRAM 120S/12 configuration CONFIG2 HIROSE-FX11LA- Configuration plug for 48bit SDRAM + 120S/12 ETH1 I/F CONFIG3 HIROSE-FX11LA- Configuration plug for 48bit SDRAM + PCI 120S/12 BRIDGE-X HIROSE-FX11LA-60S/6 PCI Bridge Mezz.– connections to GR740 GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 60: Table 8: List Of Connectors
HIROSE-FX11LA-60S/6 PCI Bridge Mezz.– connections to Bridge- Secondary BRIDGE-Y HIROSE-FX11LA-60S/6 PCI Bridge Mezz.– connections to PCI Backplane CPCI-J1 CPCI CPCI Type A CPCI connector CPCI-J2 CPCI CPCI Type B CPCI connector Table 8: List of Connectors GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 61: Figure 6-1: Front Panel View (Pins 1 Marked Red)
GR-CPCI-GR740 Figure 6-1: Front Panel View (pins 1 marked red) GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 62: Table 9: J5 Usb Type Mini Ab Connector - Ftdi Quad Serial Link
Name Comment TPFOP Output +ve TPFON Output -ve TPFIP Input +ve TPFOC Output centre-tap No connect TPFIN Input -ve TPFIC Input centre-tap No connect Table 11: J1A (Top) RJ45 10/100/1000 Mbit/s Ethernet Connector 1 GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 63: Table 12: J1B (Bottom) Rj45 10/100/1000 Mbit/S Ethernet Connector 0
□ □ GPIO10 DGND □ □ GPIO11 DGND □ □ GPIO12 DGND □ □ GPIO13 DGND □ □ GPIO14 DGND □ □ GPIO15 DGND □ □ (+3.3V) DGND Table 13: J4 PIO Header Pin out GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 64: Table 14: J5 -Header For Front Panel Dip-Switch
□ □ RX-1 □ □ TX-0 RX-0 □ □ □ □ □ □ □ □ □ □ □ □ +3.3V +3.3V □ □ DGND DGND Table 16: J7– CAN - Header for CAN Accessory board GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 65: Table 17: J8- Mil1553 - Header For Mil1553 Accessory Board
□ □ TX-A TXN-A □ □ RX-A RXN-A □ □ TX-B TXN-B □ □ RX-B RXN-B □ □ +3.3V +3.3V □ □ DGND DGND Table 17: J8– MIL1553 - Header for MIL1553 Accessory board GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 66: Table 18: Expansion Connector J9 Pin-Out (See Also Section 4.5.5)
+3.3V DGND DGND +3.3V +3.3V DGND DGND +3.3V +3.3V DGND DGND WRITEN IOSN ROMSN0 ROMSN1 +3.3V +3.3V DGND DGND BRDYN RESETN EXP_CLK DGND DGND Table 18: Expansion connector J9 Pin-out (see also section 4.5.5) GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 67: Table 19: J10- Spi Header For User Spi Interface
JTAG: TMS Table 20: J11 ASIC – JTAG Connector Name Comment VJTAG 3.3V DGND Ground B-TCK JTAG: TCK B-TDO JTAG: TDO B-TDI JTAG: TDI B-TMS JTAG: TMS Table 21: J12 PCI-Bridge – JTAG Connector GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 68: Table 22: J13 Fpga- Jtag Connector
DGND Outer Pin Return Table 23: J14 POWER – External Power Connector Name Comment +5V, typically TBD A DGND Ground +12V +12V Not used DGND Ground Table 24: J15 POWER – External Power Connector GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 69: Table 25: J16 Sodimm - 144 Pin Socket For Sdram Sodimm - Bits 31..0 & 79..64
SD_DQM0 SD_DQM1 DGND DGND +3.3V +3.3V DGND DGND SDSDA0 / pulled high SDSCL / pulled high +3.3V +3.3V Table 25: J16 SODIMM – 144 pin socket for SDRAM SODIMM – bits 31..0 & 79..64 GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 70: Table 26: J17 Sodimm - 144 Pin Socket For Sdram Sodimm - Bits 63..32 & 95..80
SD_DQM4 SD_DQM5 DGND DGND +3.3V +3.3V DGND DGND SDSDA1 / pulled high SDSCL / pulled high +3.3V +3.3V Table 26: J17 SODIMM – 144 pin socket for SDRAM SODIMM – bits 63..32 & 95..80 GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 71: List Of Oscillators, Switches And Led's
8 pole SPDT DIP switch: Pull-up/Float/Pull-Down FP-S2 GPIO[15..8] 8 pole SPDT DIP switch: Pull-up/Float/Pull-Down FP-S3 CONFIG 8 pole DIP switch (Logic '1' when 'open'): See table below Table 29: List and definition of Switches GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 72: Table 30: Dip Switch Fp-S3 Definition
PLL0 Bypassed PLL0 operational BYPASS1 PLL1 Bypassed PLL1 operational BYPASS2 PLL2 Bypassed PLL2 operational Ignore PLL lock Enable PLL lock ETH-CLK GBit 100Mbit WDOGN WDOG disconnect WDOG connect Table 30: DIP Switch FP-S3 definition GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 73: List Of Jumpers
Install to pull M66EN low, and force backplane to operate with 33MHz speed. JP24 FPGA-CFG 3x2 pin 0.1” Hdr Configuration jumpers for FPGA: see Table 3 Table 31: List and definition of PCB Jumpers (for details refer to schematic, [RD2]) GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 74: Figure 6-2: Pcb Top View
GR-CPCI-GR740 Figure 6-2: PCB Top View GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 75: Figure 6-3: Pcb Bottom View
GR-CPCI-GR740 Figure 6-3: PCB Bottom View GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 76: Figure 6-4: Pcb Top View (Photo)
GR-CPCI-GR740 Figure 6-4: PCB Top View (Photo) GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 77: Figure 6-5: Pcb Bottom View (Photo)
GR-CPCI-GR740 Figure 6-5: PCB Bottom View (Photo) GR-CPCI-GR740-UM, Sep 2017, Version 1.7 www.cobham.com/gaisler... -
Page 78: Change Record
Issue Date Section / Page Description 2015-10-12 Draft Issue 2016-01-23 Draft Issue. New Cobham Gaisler template 2016-02-26 Updated after prototype hardware 2016-06-01 §4.7 Added note concerning shared MDIO bus. §4.17 & 4.18 Removed since not relevant for rev 1.1 of the board. - Page 79 Cobham; nor does the purchase, lease, or use of a product or service from Cobham convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Cobham or of third parties.
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