Page 1 GR712RC Dual-Core LEON3FT SPARC V8 Processor 2017 User’s Manual The most important thing we build is trust GR712RC Dual-Core LEON3FT SPARC V8 Processor User’s Manual GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 2: Table Of Contents
8-bit PROM and SRAM access ................58 8- bit I/O access....................59 Burst cycles ......................59 SDRAM access ....................59 Refresh ......................... 60 5.10 Memory EDAC ....................62 5.11 Bus Ready signalling ................... 64 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 3 12.1 Overview......................90 12.2 Operation......................90 12.3 Registers....................... 91 General Purpose Register................... 93 13.1 Operation......................93 13.2 Registers....................... 93 General Purpose I/O Port .................. 94 14.1 Overview......................94 14.2 Operation......................94 14.3 Registers....................... 96 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 4 Common registers ....................151 18.7 Design considerations ..................152 18.8 Signal definitions ....................152 Obsolete......................153 19.1 Signal definitions ....................153 CAN Bus multiplexor..................154 20.1 Overview......................154 20.2 Operation......................154 20.3 Registers......................154 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 5 GRTM - CCSDS Telemetry Encoder .............. 203 27.1 Overview......................203 27.2 References......................204 27.3 Layers......................... 205 27.4 Data Link Protocol Sub-Layer ................206 27.5 Synchronization and Channel Coding Sub-Layer..........208 27.6 Physical Layer.....................211 27.7 Connectivity ....................... 213 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 6 GR712RC 27.8 Operation......................214 27.9 Registers......................217 27.10 Signal definitions ....................221 Clock Gating Unit ..................... 222 28.1 Overview......................222 28.2 Operation......................222 28.3 Registers......................223 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 7: Introduction
Scope This document is a user’s manual for the radiation-hard GR712RC Dual-Core LEON3FT SPARC V8 processor. GR712RC is based on LEON3FT and IP cores from the GRLIB IP library, implemented with the Ramon RadSafe 180 nm cell library on Tower Semiconductors 180nm CMOS process.
Page 8: Memory Map
Proprietary, do not access 0xFFF20000 - 0xFFF20100 Registers CANOC 0xFFF30000 - 0xFFF31000 Registers AHB plug&play Plug&play configuration 0xFFFFF000 - 0xFFFFFFFF Access to addresses outside the ranges described above returns an AMBA AHB error response. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 9: Interrupts
The interrupts are routed to the IRQMP interrupt controller and forwarded to the LEON3FT proces- sors. Interrupt 16-31 are generated as interrupt 12 and for those interrupts a chained interrupt handler is used. GRLIB IP cores The GR712RC uses the following cores from the GRLIB IP library: TABLE 3. Used IP cores Core Function...
Page 10: References
General purpose register 0x01 0x087 References [DS] GR712RC - Dual-Core LEON3FT SPARC V8 Processor, Data Sheet, GR712RC-DS, Issue 2.1, June 2014, Cobham Gaisler, www.cobham.com/gaisler The SPARC Architecture Manual, Version 8, Revision SAV080SI9308, SPARC  [SPARC] International Inc. ECSS - Space Engineering, SpaceWire - Links, Nodes, Routers and Networks, ...
Page 11: Errata
1 there is a window between sampling of the last bit and when the SCK clock line returns to its idle state. If a new transfer is started (a word is written to the core's transmit queue) in this window, then the bug will be triggered. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 12 Thus 80% of each device can be utilized but there will consequently be gaps in the user data. For this scheme to work with GR712RC it is mandatory that the bank size is defined as at least 4 times larger than the actual memory device mapped to the bank. Thus the gaps in the user data will be larger than the expected 20% imposed by the checkbytes, since now the distance between the start of each bank is at least four times the memory device size.
Page 13 PROM bank 1: 4 byte data starting at 0x1000 0004 => checkbyte at 0x1FFF FFFE PROM bank 1: 4 byte data starting at 0x1CCC CCC4 => checkbyte at 0x1CCC CCCE PROM bank 1: 4 byte data starting at 0x1CCC CCC8 => checkbyte at 0x1CCC CCCD GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 14 Note that the stack pointer or other cachable memory should never be used as the source operand, even if using ASI 1, since this may lead to faulty data being loaded into the data cache. Also note that GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 15 Fixed in 6.7 since release 1.0.3 1.7.9 Failing SDRAM Access After Uncorrectable EDAC Error When the memory controller of the GR712RC LEON system detects an uncorrectable EDAC error, it should respond with an AMBA ERROR response and then return to normal operation. Due to an incomplete condition check for starting new SDRAM accesses, the memory controller may perform a read access following an uncorrectable error even if there is no incoming access on the AMBA bus.
Page 16 The erratum cannot be triggered when the MCFG2.TRP field (bit 30 of MCFG2 register) is set to 1 (SDRAM t parameter is three clock cycles). VxWorks board support package for GR712RC will be updated to default MCFG2.TRP=1. For other boot loaders, please refer to the software package’s documentation for information on how to set MCFG2.TRP.
Page 17 When the MMU is enabled but TLB disabled, the MMU can in certain cases perform incorrect address translation. Therefore it is advised to never set the TLB disable bit in the MMU control regis- ter. The TLB disable bit is not set by any operating system provided by Cobham Gaisler. GR712RC-UM, Jun 2017, Version 2.9...
Page 18: Document Revision History
LSD bit description corrected in SPI controller Command regis- 23.3 2016-01-26 7.2 AHBSTAT: Remove incorrect note about AMBA ERROR over- riding correctable errors. 15.2.2 APBUART documentation mentioned receive ready instead of data ready field. Update footer GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 19 FPU trap queue has 8 entries Corrected Table 36 layout with MEMSIZE MSb Failing SDRAM Access After Uncorrectable 2014-09-04 1.7.9 Added “ EDAC Error” errata MIL-STD-1553B core duplicate interrupt asser- Added “ 1.7.10 tion” errata GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 20 Note on EDAC usage with 8-bit wide memory introduced 3.3, 21.3 Mil-Std-1553B clocking clarified DLLBPN polarity corrected Delay line explained, figure added 4.2.12, 4.6.1, MMU and cache handling clarified 4.6.3 SDRAM example programming clarified 15.3 UART baud rate generation clarified GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 21 Updated all sections with additional details 2010-11-09 Corrected typos in address map 2010-07-30 Re-ordered chapters, improved description of clocking 2010-03-31 Refined text to describe only the GR712RC config 2009-06-23 Added GRTIMER, updated GRTM and IRQs 2009-05-19 Corrected bus timing register 2009-04-07 Added separate chapters for clocking and I/O switch matrix.
Page 22: Signals And I/O Switch Matrix
GR712RC Signals and I/O Switch Matrix The GR712RC is housed in a 240-pin ceramic quad-flat pack package (CQFP-240). To fit in this package, some of the on-chip peripheral functions have to share I/O pins. A programmable I/O switch matrix provides access to several I/O units. When an interface is not activated, its pins automatically become general purpose I/O.
Page 23 CANTXA High-Z CAN Transmit A GPIO[13] High-Z In/Out GPIO 1 Register, bit 13 SWMX[17] SPW_TXD[2] High High-Z SpaceWire Transmit Data 2 CANTXB High-Z CAN Transmit B GPIO[14] High-Z In/Out GPIO 1 Register, bit 14 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 24 SWMX[32] 1553TXNA High-Z MIL-STD-1553B Transmit Negative A High-Z Proprietary, enabled by CAN RMTXEN High High-Z Ethernet Transmit Enable GPIO[29] High-Z In/Out GPIO 1 Register, bit 29 SWMX[33] 1553TXINHA High High-Z MIL-STD-1553B Transmit Inhibit A GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 25 At reset, bits 11 and 3 in the clock divisor reg- divisor registers ister of the SpaceWire interfaces are set from this input SWMX[46] TCCLK[3] Rising Telecommand Clock 3 GPIO[43] GPIO 2 Register, bit 11 (input only) GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 26 GPIO 2 Register, bit 29 SWMX[65] CB[14] High-Z In/Out Reed-Solomon Check Bit 14 GPIO[62] High-Z In/Out GPIO 2 Register, bit 30 SWMX[66] CB[15] High-Z In/Out Reed-Solomon Check Bit 15 GPIO[63] High-Z In/Out GPIO 2 Register, bit 31 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 27 SpaceWire Receive Strobe 2 SWMX[17] SPW_TXD[2] High High-Z SpaceWire Transmit Data 2 SWMX[16] SPW_TXS[2] High High-Z SpaceWire Transmit Strobe 2 SWMX[23] SPW_RXD[3] High SpaceWire Receive Data 3 SWMX[22] SPW_RXS[3] High SpaceWire Receive Strobe 3 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 28 SWMX[57] I2CSDA High-Z In/Out I2C Serial Data SWMX[58] I2CSCL High-Z In/Out I2C Serial Clock SWMX[44] SPICLK High-Z SPI Clock SWMX[45] SPIMOSI High-Z SPI Master Out Slave In SWMX[51] SPIMISO SPI Master In Slave Out GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 29 Rising Telecommand Clock 4 SWMX[58] TCD[4] Telecommand Data 4 SWMX[56] TCRFAVL[4] High Telecommand RF Available 4 SWMX[9] TMCLKI Rising Telemetry Clock Input SWMX[10] TMCLKO High-Z Telemetry Clock Output SWMX[8] TMDO High-Z Telemetry Data Out GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 30 GPIO pin alternative. The first GRGPIO core is mapped on GPIO[31:0], and the second GPIO core is mapped on GPIO[63:32]. Also note that when the CAN core is enabled, the output of pins 172, GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 31 1553 interface, but since this interface has a higher priority, the two interfaces are not considered con- flicting in the case they are both enabled simultaneously. The pins listed in table 10 have fixed functions that are not connected to the switch matrix. TABLE 10. GR712RC fixed pins Interface GR712RC pin...
Page 32: Clocking
GR712RC Clocking The table below specifies the clock inputs to the GR712RC. TABLE 11. Clock inputs Clock input Description INCLK System clock input SPWCLK SpaceWire clock TMCLKI Telemetry transponder clock (input shared with UART4) 1553CK 1553 clock (input shared with Ethernet and TC)
Page 33: Mil-Std-1553
12 MHz if a 50% duty cycle is necessary. If the SLINK clock duty cycle does not need to be 50% any multiple of 6 MHz is possible. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 34: Sdram Clock
Read data Clock gating unit The GR712RC device has a clock gating unit through which individual cores can have their AHB clocks enabled/disabled and resets driven. The cores connected to the clock gating unit are listed in the table below: Table 13.
Page 35: Test Mode Clocking
For more information see the chapter about the clock gating unit. 3.10 Test mode clocking When in test mode (TESTEN signal = 1) all clocks in the design are connected to the INCLK test clock. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 36: Leon3Ft - High-Performance Sparc V8 32-Bit Processor
LEON3FT - High-performance SPARC V8 32-bit Processor Overview The GR712RC implements two LEON3FT processor cores in SMP configuration. LEON3FT is a 32- bit processor core conforming to the IEEE-1754 (SPARC V8) architecture. It is designed for embed- ded applications, combining high performance with low complexity and low power consumption.
Page 37: Leon3 Integer Unit
4.1.9 Multi-processor support LEON3 is designed to be use in multi-processor systems and the GR712RC contains two cores. Each processor has a unique index to allow processor enumeration. The write-through caches and snooping mechanism guarantees memory coherency in shared-memory systems.
Page 38 ME (Memory): Data cache is accessed. Store data is written to the data cache at this time. XC (Exception) Traps and interrupts are resolved. For cache reads, the data is aligned. WR (Write): The result of any ALU or cache operations are written back to the register file. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 39 Full support for SPARC V8 divide instructions is provided (SDIV, UDIV, SDIVCC & UDIVCC). The divide instructions perform a 64-by-32 bit divide and produce a 32-bit result. Rounding and overflow detection is performed as defined in the SPARC V8 standard. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 40 30-bit time tag The operation and control of the trace buffer is further described in section 9.4. Note that in GR712RC, each processor has its own trace buffer allowing simultaneous tracing of both instruction streams. GR712RC-UM, Jun 2017, Version 2.9...
Page 41 If set, the SPARC V8 multiply and divide instructions are available. Hardcoded to 1. [7:5]: Number of implemented watchpoints. Hardcoded to 2 [4:0]: Number of implemented registers windows corresponds to NWIN+1. Hardcoded to 7. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 42 When enabled, any taken trap will always jump to the reset trap handler (%tbr.tba + 0). The trap type will be indicated in %tbr.tt, and must be decoded by the shared trap handler. SVT is enabled by setting bit 13 in %asr17. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 43 The power-down mode is entered by performing a WRASR instruction to %asr19: wr %g0, %asr19 During power-down, the pipeline is halted until the next interrupt occurs. The processor clock is gated, reducing power consumption from dynamic switching of logic and clock net. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 44: Instruction Cache
ET=0, S=1 4.2.15 Multi-processor support The GR712RC contains two LEON3 processor support symmetric multiprocessing (SMP) configura- tion. After reset, only the first processor will start while the second processor will remain halted in power-down mode. After the system has been initialized, the second processor can be started by writ- ing to the ‘MP status register’, located in the multi-processor interrupt controller.
Page 45: Data Cache
Data cache tag A data cache tag entry consists of several fields as shown in figure 7: Tag for 4 KiB way, 16 bytes/line ATAG 000000 VALID Figure 7. Data cache tag layout Field Definitions: GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 46: Additional Cache Functionality
DS bit in the cache control register. When enabled, the data cache monitors write accesses on the AHB bus to cacheable locations. If an other AHB master writes to a cacheable location which is cur- rently cached in the data cache, the corresponding cache line is marked as invalid. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 47 [29:28]: Cache replacement policy (REPL). 00 - no replacement policy (direct-mapped cache), 01 - least recently used (LRU), 10 - least recently replaced (LRR), 11 - random [27]: Cache snooping (SN). Set if snooping is implemented. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 48: Memory Management Unit
MMU is enabled, the caches tags store the virtual address and also include an 8-bit context field. On cache miss or access to an uncacheable location, the virtual address is translated to a physical address before the access appears on the AHB bus. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 49 [31:12] Address tag. The physical address tag of the cache line. [1]: Parity. The odd parity over the snoop tag (ATAG field. [0]: Snoop hit. When set, the cache line is not valid and will cause a cache miss if accessed by the processor. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 50: Floating-Point Unit
GR712RC Floating-point unit Each of the LEON3 processor in GR712RC contains a high-performance GRFPU floating-point unit. The GRFPU operates on single- and double-precision operands, and implements all SPARC V8 FPU instructions. The FPU is interfaced to the LEON3 pipeline using a LEON3-specific FPU controller (GRFPC) that allows FPU instructions to be executed simultaneously with integer instructions.
Page 51 For very small programs, the only risk of error build-up is if a part of the applica- GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 52: Signal Definitions
When the processor enters error mode, the ERRORN output is driven active low, else it is in tri-state and therefore requires an additional external pull-up. The signals are described in table 23. Table 23. Signal definitions Signal name Type Function Active ERRORN Tri-state output Processor error mode indicator GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 53: Fault Tolerant Memory Controller
Figure 15 below shows how the connection to the different device types is made. ROMSN[1 :0] PROM WRITEN IOSN FTMCTRL RAMSN[1:0] SRAM RAMOEN RAMWEN SDCSN[1:0] SDRAM SDRASN SDCASN SDWEN SDDQM[3:0] ADDRESS[23:0] DATA[31:0] CB[15:0] Figure 15. FTMCTRL connected to different types of memory devices GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 54: Prom Access
Figure 16. Prom non-consecutive read cyclecs. data1 data2 data1 data2 data lead-out sdclk address romsn data Figure 17. Prom consecutive read cyclecs. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 55 Figure 18. Prom read access with two waitstates. lead-in data lead-out sdclk address romsn writen data Figure 19. Prom write cycle (0-waitstates) data lead-out lead-in data data sdclk address romsn writen data Figure 20. Prom write cycle (2-waitstates) GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 56: Memory Mapped Io
21. The data2 phase is extended when waitstates are added. lead-in data1 data2 lead-out sdclk address iosn data Figure 21. I/O read cycle (0-waitstates) lead-in data lead-out sdclk address iosn writen data Figure 22. I/O write cycle (0-waitstates) GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 57: Sram Access
Waitstates are added in the same way as for PROM. The GR712RC uses a common SRAM write strobe (RAMWEN), and the read-modify-write bit MCFG2 must be set to enable read-modify-write cycles for sub-word writes.
Page 58: 8-Bit Prom And Sram Access
Table 24. Supported SRAM and PROM width, EDAC and RMW combinations Bus width EDAC RMW bit (SRAM only) None None 32+7 The RMW bit in MCFG2 must not be set if RAM EDAC is dissembled when RAM width is set to 8- bit. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 59: 8- Bit I/O Access
13 row-address bits. The size of the two banks can be programmed in binary steps between 4MiB and 512MiB. The total maximum supported SDRAM capacity is 1 GiB. The operation of the SDRAM controller is controlled through MCFG2 and MCFG3 (see below). GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 60: Refresh
CL=2; TRP=0, TCAS=0, TRFC=4 CL=3; TRP=0, TCAS=1, TRFC=4 Refresh The SDRAM controller contains a refresh function that periodically issues an AUTO-REFRESH command to both SDRAM banks. The period between the commands (in clock periods) is pro- GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 61 Initialisation Each time the SDRAM is enabled (bit 14 in MCFG2), an SDRAM initialisation sequence will be sent to both SDRAM banks. The sequence consists of one PRECHARGE, eight AUTO-REFRESH and one LOAD-COMMAND-REGISTER command. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 62: Memory Edac
RB (read bypass) is set, the memory checkbits of the loaded data will be stored in the TCB field during memory read cycles. NOTE: when the EDAC is enabled, the RMW bit in memory configura- tion register 2 must be set. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 63 (i.e. interleaved depth I=2) with the following mapping to the 32- bit data and 16-bit checksum, were c is a symbol with codeword index i and symbol index j: = DATA[31:28] = DATA[27:24] GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 64: Bus Ready Signalling
I/O accesses. Figure 28 shows the use of BRDYN with asynchronous sampling. BRDYN is kept asserted for more than 1.5 clock-cycle. Two synchronization registers are used so it will take at least one additional GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 65: External Bus Errors
8-bit mode for RAM and PROM. That is, when four bytes are written for a word access to 8-bit wide memory BEXCN is only sampled in the last access with the same tim- ing as a single access in 32-bit mode. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 66: Read Strobe
Table 28. FTMCTRL memory controller registers APB Address offset Register 0x80000000 Memory configuration register 1 (MCFG1) 0x80000004 Memory configuration register 2 (MCFG2) 0x80000008 Memory configuration register 3 (MCFG3) 0x8000000C Memory configuration register 4 (MCFG4) GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 67 RAM BANK SIZE RBRDY RMW RAM WIDTH RAM WRITE WS RAM READ WS SDRAM refresh (SDRF) - Enables SDRAM refresh. SDRAM TRP parameter (TRP) - t will be equal to 2 or 3 system clocks (0/1). GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 68 Test checkbits (TCB) - This field replaces the normal checkbits during write cycles when WB is set. It is also loaded with the memory checkbits during read cycles when RB is set. The period between each AUTO-REFRESH command is calculated as follows: = ((reload value) + 1) / SYSCLK REFRESH GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 69: Signal Definitions
Any SDDQM[ ] signal can be used for CB[ ]. GPIO[3] / Input Configuring PROM data width at reset. 8-bit data width SWMX[6] when “0”, and 32-bit when “1”. GPIO[1] / Input Enabling EDAC usage for PROM at reset when “1”. SWMX[4] GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 70: On-Chip Memory With Edac Protection
On-chip Memory with EDAC Protection Overview The GR712RC is provided with 192 KiB on-chip RAM, based on the FTAHBRAM core from GRLIB. The RAM is protected with an error detection and correction unit (EDAC), capable of cor- recting one error per word, and detecting two errors per word. The on-chip memory is not cacheable.
Page 71: Registers
Test Check Bits (TCB): Used as checkbits when the WB bit is set during writes and loaded with the check bits during a read operation when the RB bit is set. Any unused most significant bits are reserved. Always read as ‘000...0’. All fields except TCB are initialized to 0 at reset. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 72: Ahb Status Registers
2: 0 The HSIZE signal of the AHB transaction that caused the error Table 39. AHB Failing address register AHB FAILING ADDRESS 31: 0 The HADDR signal of the AHB transaction that caused the error. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 73: Multiprocessor Interrupt Controller
8.2.1 Interrupt routing The GR712RC device has an internal interrupt bus consisting of 31 interrupts, which are mapped on the 15 SPARC interrupts by the IRQMP controller. The lowest 15 interrupts (1 - 15) are mapped directly on the 15 SPARC interrupts. When any of these lines are asserted high, the corresponding bit in the interrupt pending register is set.
Page 74 15 cannot be maskable by the LEON3 processor and should be used with care - most operating sys- tems do not safely handle this interrupt. 8.2.3 Interrupt assignment The following table specifies the interrupt assignment for the GR712RC: TABLE 40. Interrupt assignment Core Interrupt #...
Page 75: Registers
Interrupt Level n (IL[n]): Interrupt level for interrupt n. Reserved. 8.3.2 Interrupt pending register EIP[31:16] IP[15:1] Figure 34. Interrupt pending register [31:17] Extended Interrupt Pending n (EIP[n]). [15:1] Interrupt Pending n (IP[n]): Interrupt pending for interrupt n. Reserved GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 76 Processor interrupt mask register EIM[31:16] IM[15:1] Figure 38. Processor interrupt mask register [31:16] Interrupt mask for extended interrupts [15:1] Interrupt Mask n (IM[n]): If IMn = 0 the interrupt n is masked, otherwise it is enabled. Reserved. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 77 IFC[n] and the previous state of IF[n]. Reserved. 8.3.9 Extended interrupt identification register EID[4:0] Figure 41. Extended interrupt identification register [4:0] ID (16 - 31) of the acknowledged extended interrupt. Read only. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 78: Hardware Debug Support Unit
Debug Support Unit (DSU). The DSU acts as an AHB slave and can be accessed by any AHB master. In the GR712RC, an external debug host can access the DSU through JTAG or SpaceWire links 0 and 1 (using RMAP).
Page 79: Ahb Trace Buffer
EN bit is reset, or when a AHB breakpoint is hit. Tracing is temporarily suspended when the processor enters debug mode. Note that neither the trace buffer memory nor the breakpoint registers (see below) can be read/written by software when the trace buffer is enabled. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 80: Instruction Trace Buffer
During the instruc- tion tracing (processor in normal mode) the trace buffer and the trace buffer control register can not be accessed. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 81: Dsu Memory Map
%ln : 0x300000 + (((psr.cwp * 64) + 64 + n*4) mod (NWINDOWS*64)) • %in : 0x300000 + (((psr.cwp * 64) + 96 + n*4) mod (NWINDOWS*64)) • %gn : 0x300000 + (NWINDOWS*64) • %fn : 0x301000 + n*4 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 82: Dsu Registers
This register controls all processors in a multi-processor system, and is only accessible in the DSU memory map of processor 0..Figure 45. DSU Debug Mode Mask register GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 83 Break (BR). If set, the processor will be put in debug mode when AHB trace buffer stops due to AHB breakpoint hit. [31:16] Trace buffer delay counter (DCNT). Note that the number of bits actually implemented depends on the size of the trace buffer. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 84 RESERVED IT POINTER Figure 52. Instruction trace control register [15:0] Instruction trace pointer. Note that the number of bits actually implemented depends on the size of the trace buffer. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 85: Jtag Debug Interface
Write (W) - ‘0’ - read transfer, ‘1’ - write transfer 33 32 AHB transfer size - “00” - byte, “01” - half-word, “10” - word, “11”- reserved 31 30 AHB address Table 46. JTAG debug link Data register AHB DATA GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 86: Registers
NOTE: for correct operation, all JTAG signals should be pulled-up externally with 10kOhm. The GR712RC does not include any internal pull-ups. This is in line with the TAP specification where TMS and TDI implementation should be such that if an external signal fails (e.g. open circuit) then the behavior of TMS and TDI should be equivalent to a logical 1 input.
Page 87: General Purpose Timer Unit
The interrupt pending bit is only set when the interrupt is enabled for that timer. Note: The WDOGN signal cannot be used if the system is clocked using the 2x DLL, but only when the system is clocked directly from INCLK. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 88: Registers
Separate interrupts (SI). Reads ‘1’ to indicate the timer unit generates separate interrupts for each timer. 7: 3 Interrupt ID of first timer. Set to 8. Read-only. 2: 0 Number of implemented timers. Set to 4. Read-only. Table 52. Timer counter value register TIMER COUNTER VALUE GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 89: Signal Definitions
Table 55. Signal definitions Signal name Type Function Active wdogn Tri-state output Watchdog output. Equivalent to interrupt pend- ing bit of last timer. Can NOT be used when system clock is generated from 2x DLL. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 90: General Purpose Timer Unit With Time Latch Capability
The likelihood is approximately 1/(prescaler reload value). Note that the latch function cannot be used with the core’s own interrupt number 7. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 91: Registers
Separate interrupts (SI). Set to 0 to indicate common interrupt (7) for each timer. Read-only. Interrupt ID of first timer. Set to 7. Read-only. Number of implemented timers. Set to 2. Read-only. Table 60. Timer latch configuration register SELECT GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 92 Restart (RS): If set the value from the timer reload register is loaded to the timer counter value regis- ter and decrementing the timer is restarted. Enable (EN): Enable the timer. Table 64. Timer latch registers LTCV Latched Timer Counter Value (LTCV). Value latch from corresponding timer. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 93: General Purpose Register
TM clock select: 0 - TMCLKI, 1 - System clock 2 - 1: SpaceWire clock select: 0 - 1X, 1 - System clock, 2 - 2X, 3 - 4X SpaceWire clock source: 0 - SPWCLK, 1 - INCLK This register resets to 0. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 94: General Purpose I/O Port
General Purpose I/O Port 14.1 Overview The GR712RC contains two 32-bit GPIO ports, providing up to 64 controllable I/O signals. The I/O signals also have alternative functions when connected to the various on-chip peripherals, and can also serve as external interrupts inputs.
Page 95 GRGPIO - 2 GPIO[45] SWMX[48] In/Out GRGPIO - 2 GPIO[46] SWMX[49] In/Out GRGPIO - 2 GPIO[47] SWMX[50] GRGPIO - 2 GPIO[48] SWMX[51] GRGPIO - 2 GPIO[49] SWMX[52] In/Out GRGPIO - 2 GPIO[50] SWMX[53] In/Out GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 96: Registers
I/O port output value Table 71. I/O port direction register I/O port direction value I/O port direction value (0=output disabled, 1=output enabled). Input-only bits are don’t care. Table 72. Interrupt mask register Interrupt mask GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 97: Signal Definitions
Table 74. Interrupt edge register Interrupt edge Interrupt edge (0=level, 1=edge) 14.4 Signal definitions The signals are described in table 75. Table 75. Signal definitions Signal name Type Function Active GPIO[63:0] Input/Output General purpose input output GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 98: Uart Serial Interface
15.1 Overview The GR712RC contains six UART interfaces for asynchronous serial communications. The UARTs supports data frames with 8 data bits, one optional parity bit and one stop bit. To generate the bit-rate, each UART has a programmable 12-bit clock divider. Two 8-byte FIFOs are used for data transfer between the APB bus and UART.
Page 99: Baud-Rate Generation
It is then possible to perform loop back tests to verify operation of receiver, transmitter and associated software routines. In this mode, the outputs remain in the inactive state, in order to avoid sending out data. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 100: Fifo Debug Mode
0x80100300 UART 3 0x80100400 UART 4 0x80100500 UART 5 Table 77. UART registers APB address offset Register UART Data register UART Status register UART Control register UART Scaler register 0x10 UART FIFO debug register GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 101 Transmitter FIFO empty (TE) - indicates that the transmitter FIFO is empty. Transmitter shift register empty (TS) - indicates that the transmitter shift register is empty. Data ready (DR) - indicates that new data is available in the receiver holding register GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 102: Signal Definitions
Receiver holding register or FIFO (write access) 15.8 Signal definitions The signals are described in table 83. Table 83. Signal definitions Signal name Type Function Active UART_TX[5:0] Output UART transmit data line UART_RX[5:0] Input UART receive data line GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 103: Spacewire Interface With Rmap Support
The SpaceWire interface is configured through a set of registers accessed through an APB interface. Data is transferred through DMA channels using an AHB master interface. GR712RC includes six GRSPW2 cores. Only cores GRSPW2-0 and GRSPW2-1 include RMAP sup- port. Each core includes a single DMA channel. Each core supports a single port.
Page 104: Link Interface
N-Char FIFO. FCTs are sent as long as the outstanding counter is less than or equal to 48 and there are at least 8 more empty FIFO entries than the counter value. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 105 62. L-Chars are the handled automatically by the host domain link interface part while all N-Chars are stored in the receiver FIFO for further handling. If two or more consecutive EOPs/EEPs are received all but the first are discarded. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 106: Receiver Dma Channels
It is possible to have both the time-transmission and reception functions enabled at the same time. 16.4 Receiver DMA channels The receiver DMA engine handles reception of data from the SpaceWire network to different DMA channels. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 107 At least 2 non EOP/EEP N-Chars needs to be received for a packet to be stored to the DMA channel. If it is an RMAP packet with hardware RMAP enabled 3 N-Chars are needed since the command byte determines where the packet is processed. Packets smaller than these sizes are discarded. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 108 Channel enabled Last DMA channel Separate addressing RMAP enabled dma(n).addr* !dma(n).mask= defaddr*!defmask = rxaddr*!dma(n).mask rxaddr*!defmask Process RMAP Store packet to Discard packet DMA channel command Figure 63. Flow chart of packet reception. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 109 A descriptor is enabled by setting the address pointer to point at a location where data can be stored and then setting the enable bit. The WR bit can be set to cause the selector to be set to zero when GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 110 ‘0’ and the nospill bit is ‘0’ the packets will be discarded. If nospill is one the GRSPW waits until rxdescav is set and the characters are kept in the N-Char fifo during this time. If the fifo becomes full further N-char transmissions are inhibited by stopping the transmission of FCTs. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 111 If an AHB error occurs during reception the current packet is spilled up to and including the next EEP/EOP and then the currently active channel is disabled and the receiver enters the idle state. A bit in the channels control/status register is set to indicate this condition. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 112: Transmitter Dma Channels
DC bit should be set for the data field. This field is only used by the GRSPW when the CRC logic is available. The header CRC will be calculated from the data fetched from the GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 113 31: 0 Header address (HEADERADDRESS) - Address from where the packet header is fetched. Does not need to be word aligned. Table 88. GRSPW transmit descriptor word 2 (address offset 0x8) 24 23 RESERVED DATALEN GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 114 Then a new descriptor is read and if enabled a new transmission starts, otherwise the transmit enable bit is cleared and nothing will happen until it is enabled again. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 115: Rmap
The Remote Memory Access Protocol (RMAP) is used to implement access to resources in the node via the SpaceWire Link. Some common operations are reading and writing to memory, registers and FIFOs. The GRSPW has an optional hardware RMAP command handler which on the GR712RC is GR712RC-UM, Jun 2017, Version 2.9...
Page 116 If there is a mismatch and a reply has been requested the error code in the reply is set to 3. Replies are sent if and only if the ack field is set to ‘1’. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 117 Non-verified writes have no restrictions when the incrementing bit is set to 1. If it is set to 0 the num- ber of bytes must be a multiple of 4 and the address word aligned. There is no guarantee how many words will be written when early EOP/EEP is detected for non-verified writes. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 118 The last control option for the command handler is the possibility to set the destination key which is found in a separate register. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 119 If alignment is before writ- violated nothing is done and ing, send error code is set to 10. If an AHB acknowledge error occurs error code is set to 1. Reply is sent. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 120: Amba Interface
A burst is always started when the FIFO is half-empty or if it can hold the last data for the packet. The burst containing the last data might have shorter length if the packet is not an even number of bursts in size. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 121: Spacewire Clock Generation
Pins (MSB-LSB) SWMX45, 43, 40 and 37 are used for this. Thus it is possible to use a SPW- CLK which is any multiple of 10 between 10-100 MHz (note that the required precision is 10 MHz +/ - 1 MHz). GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 122: Registers
The SpaceWire transmitter uses SDR output registers meaning that the bitrate will be equal to the transmit clock. The SpaceWire input signals are sampled synchronously with DDR registers using the transmit clock. This allows the GR712RC to receive SpaceWire data at a bitrate equal to the transmit clock.
Page 123 Link Start (LS) - Start the link, i.e. allow a transition from ready to started state. Reset value: ‘1’ on links 0 - 1, ‘0’ on links 2 - 5. Link Disable (LD) - Disable the SpaceWire codec. Reset value: ‘0’. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 124 Clock divisor run (CLKDIVRUN) - Clock divisor value used for the clock-divider when the link- interface is in the run-state. The actual divisor value is Clock Divisor register + 1. Reset value: "0000" & SWMX[45] & SWMX[43] & SWMX[40] & SWMX[37] GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 125 Transmit interrupt (TI) - If set, an interrupt will be generated each time a packet is transmitted, if the interrupt enable (IE) bit in the corresponding transmit descriptor is set as well. The interrupt is gener- ated regardless of whether the transmission was successful or not. Not reset. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 126 7: 0 Address (ADDR) - Address used for node identification on the SpaceWire network for the corre- sponding dma channel when the EN bit in the DMA control register is set. Reset value: 254. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 127: 16.10 Signal Definitions
Table 105.Signal definitions Signal name Type Function Active SPWCLK Input SpaceWire receiver and transmitter clock SPW_RXD[] Input Data input High SPW_RXS[] Input Strobe input High SPW_TXD[] Output Data output High SPW_TXS[] Output Strobe output High GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 128: Ethernet Media Access Controller (Mac)
100 Mbit. The minimum AHB clock for 10 Mbit operation is 2.5 MHz, while 18 MHz is needed for 100 Mbit. Using a lower AHB clock than specified will lead to excessive packet loss. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 129: Tx Dma Interface
The pointer will automatically wrap back to zero when the next 1 kB boundary has been reached (the descriptor at address offset 0x3F8 has been used). The WR bit in the descriptors can be set to make the pointer wrap back to zero before the 1 kB boundary. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 130: Rx Dma Interface
RESERVED Length error (LE) - The length/type field of the packet did not match the actual number of received bytes. Overrun error (OE) - The frame was incorrectly received due to a FIFO overrun. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 131 Packets larger than maximum size cause the FT bit in the receive descriptor to be set. The length field is not guaranteed to hold the correct value of received bytes. The counting stops after the word con- taining the last byte up to the maximum size limit has been written to memory. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 132: Mdio Interface
The core is programmed through registers mapped into APB address space. Table 111.GRETH registers APB address Register 0x80000E00 Control register 0x80000E04 Status/Interrupt-source register 0x80000E08 MAC Address MSB 0x80000E0C MAC Address LSB 0x80000E10 MDIO Control/Status 0x80000E14 Transmit descriptor pointer 0x80000E18 Receiver descriptor pointer GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 133 Transmitter error (TE) - A packet was transmitted which terminated with an error. Cleared when written with a one. Not Reset. Receiver error (RE) - A packet has been received which terminated with an error. Cleared when writ- ten with a one. Not Reset. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 134 Transmitter descriptor table base address (BASEADDR) - Base address to the transmitter descriptor table.Not Reset. 9: 3 Descriptor pointer (DESCPNT) - Pointer to individual descriptors. Automatically incremented by the Ethernet MAC. 2: 0 RESERVED GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 135: Signal Definitions
Ethernet Receive Data 1 RMCRSDV Input Ethernet Carrier Sense / Data Valid High RMINTN Input Ethernet Management Interrupt RMMDIO Input/Output Ethernet Media Interface Data RMMDC Output Ethernet Media Interface Clock High RMRFCLK Input Ethernet Reference Clock GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 136: Can Interface
Note: The CAN bus multiplexer has to be programmed to activate OC-CAN1 and OC-CAN2 on the GR712RC can bus A and can bus B. The OC-CAN1 and OC-CAN2 are disabled at reset by CAN- MUX (see section 20 for further information).
Page 137: Basiccan Mode
RX data byte 6 RX data byte 6 RX data byte 7 RX data byte 7 RX data byte 8 RX data byte 8 (0x00) (0x00) Clock divider Clock divider Clock divider Clock divider GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 138 If there is another message waiting in the FIFO a new receive interrupt will be generated (if enabled) and the receive buffer status bit will be set again. To clear the Data overrun status bit CMR.3 must be written with 1. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 139 BasicCAN mode. This core resets the receive interrupt bit when the release receive buffer command is given (like in PeliCAN mode). Also note that bit IR.5 through IR.7 reads as 1 but IR.4 is 0. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 140 The top 8 bits of the 11 bit identifier are compared with the acceptance code register only comparing the bits set to zero in the acceptance mask register. If a match is detected the message is stored to the fifo. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 141: Pelican Mode
Clock divider Clock divider Clock divider The transmit and receive buffers have different layout depending on if standard frame format (SFF) or extended frame format (EFF) is to be transmitted/received. See the specific section below. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 142 The Self reception request bit together with the self test mode makes it possible to do a self test of the core without any other cores on the bus. A message will simultaneously be transmitted and received and both receive and transmit interrupt will be generated. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 143 Set when the transmit buffer is released IR.0 Receive interrupt Set while the fifo is not empty. This register is reset on read with the exception of IR.0 which is reset when the fifo has been emptied. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 144 ECC register will not change value until it has been read out. The table below shows how to inter- pret bit 7-6 of ECC. Table 135.Error code interpretation ECC.7-6 Description Bit error Form error Stuff error Other GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 145 255 to this register. Note that unlike the SJA1000 this core will signal bus-off immediately and not first when entering operating mode. The bus-off recovery sequence starts when entering operating mode after writing 255 to this register in reset mode. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 146 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID.20 ID.19 ID.18 Bit 7:5 - Bottom three bits of an SFF identifier. Bit 4:0 - Don’t care. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 147 Data field For SFF frames the data field is located at address 19 to 26 and for EFF frames at 21 to 28. The data is transmitted starting from the MSB at the lowest address. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 148 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID.20 ID.19 ID.18 Bit 7:5 - Bottom three bits of an SFF identifier. Bit 4 - 1 if RTR frame. Bit 3:0 - Always 0. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 149 In total eight registers are used for the acceptance filter as shown in the table below. Note that they are only read/writable in reset mode. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 150 Dual filter mode, extended frame When receiving a standard frame in dual filter mode the registers ACR0-3 are compared against the incoming message in the following way: GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 151: Common Registers
The CAN core system clock is calculated as: = 2*t *(BRP+1) where t is the system clock. The sync jump width defines how many clock cycles (t ) a bit period may be adjusted with by one re-synchronization. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 152: Design Considerations
The core transmits active error frames in Listen only mode 18.8 Signal definitions The signals are described in table 155. Table 155.Signal definitions Signal name Type Function Active CANTX[] Output CAN transmit data CANRX[] Input CAN receive data GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 153: Obsolete
GR712RC Obsolete Proprietary function not supported. 19.1 Signal definitions The signals are described in table 156. Table 156.Signal definitions Signal name Type Function Active Output Proprietary Output Proprietary Output Proprietary Output Proprietary Output Proprietary GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 154: Can Bus Multiplexor
BUSA 31: 2 RESERVED Bus B select (BUSB) - 0, unused. 1, OC-CAN2 on bus B. 0 on reset. Bus A select (BUSA) - 0, unused. 1, OC-CAN1 on bus A. 0 on reset. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 155: Mil-Std-1553B Bc/Rt/Bm
16 for RT command legalization. The core generates interrupt 14. B1553BRM Actel Core1553BRM Core1553BRM signals 1553 signals CPU IF MEM IF Control AHB slave IF AHB master IF registers AMBA AHB Figure 67. Block diagram GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 156: Ahb Interface
] has been translated into requirements on arbitration latency and access time for 1553BRM the B1553BRM core on the AMBA on-chip bus. This takes into account the transfer between clock domains and translation into AMBA accesses that are done inside the B1553BRM core. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 157 The B1553BRM and GRETH cores have elevated priority in the GR712RC arbiter over all other AMBA masters, meaning that for latency calculation the B1553BRM will only have to wait for the currently active master to complete its access before getting access to the AMBA bus.
Page 158: Registers
Interrupt level. Controls the intlevel input signal of the Core1553BRM core. AHB page address register abits ahbaddr RESERVED Figure 70. AHB page address register [31:17]: Holds the top most bits of the AHB address of the allocated memory area. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 159: Signal Definitions
1553TXA Output Negative data to the A transmitter 1553TXNA Output Inhibit for the B transmitter High 1553TXINHB Output Positive output to the B transmitter High 1553TXB 1553TXNB Output Negative output to the B transmitter GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 160: I2C-Master
STOP condi- tion to complete the transfer. Section 22.2.4 contains three more example transfers from the perspec- tive of a software driver. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 161 To write a byte to a slave the I C-master must generate a START condition and send the slave address with the R/W bit set to ‘0’. After the slave has acknowledged the address, the master transmits the GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 162 To perform sequential reads the master can iterate over steps 13 - 15 by not setting the ACK and STO bits in step 13. To end the sequential reads the ACK and STO bits are set. Consult the documentation of the I C-slave to see if sequential reads are supported. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 163: Registers
Clock prescale register 0x80000C04 Control register 0x80000C08 Transmit register* 0x80000C08 Receive register** 0x80000C0C Command register* 0x80000C0C Status register** * Write only ** Read only Table 165. I C-master Clock prescale register RESERVED Clock prescale GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 164 Acknowledge (ACK) - Used when acting as a receiver. ‘0’ sends an ACK, ‘1’ sends a NACK. RESERVED Interrupt acknowledge (IACK) - Clears interrupt flag (IF) in status register. Table 170. I C-master status register RESERVED RxACK BUSY RESERVED 31: 8 RESERVED GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 165: Signal Definitions
22.4 Signal definitions The signals are described in table 171. Table 171.Signal definitions Signal name Type Function Active I2CSCL Input/Output C clock line I2CSDA Input/Output C data line GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 166: Spi Controller
SPICLK. The figure does not include the SPIMISO sig- nal, the behavior of this line is the same as for the SPIMOSI signal. However, due to synchronization issues the SPIMISO signal will be delayed when the core is operating in slave mode. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 167 Mode register fields DIV16, FACT, and PM. Without DIV16 the SPICLK frequency is: AMBAclockfrequency -------------------------------------------------------------------- - SCKFrequency         – 2 FACT With DIV16 enabled the frequency of SPICLK is derived through: GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 168: Registers
6: 0 Core revision (REV) - This manual applies to core revision 2. Table 174. SPI controller Mode register LOOP CPOL CPHA DIV16 RESERVED FACT RESERVED GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 169 LST bit in the Command register has been written. This bit is cleared by writing ‘1’, writes of ‘0’ have no effect. RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 170 Event register bit has been set and is always read as zero. 21: 0 RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility. Table 178. SPI controller Transmit register TDATA GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 171: Signal Definitions
REV = ‘0’ - 0x0000FF00 REV = ‘1’ - 0x00FF0000 23.4 Signal definitions The signals are described in table 180. Table 180.Signal definitions Signal name Type Function Active SPICLK Output SPI clock SPIMISO Input Master-Input-Slave-Output SPIMOSI Output Master-Output-Slave-Input GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 172: Slink Serial Bus Based Real-Time Network Master
An unsolicited word sent from a slave that is not an INTERRUPT nor a response to a READ command. SEQUENCE The master performs a sequence of operations described by an in- memory array which has a maximum size of 1024 elements. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 173 Array A Base Address register. The base address of array B is written to the Array B Base Address Register. Software enables processing of the SEQUENCE operations by setting the SEQUENCE Enable (SE) bit and initializing the SEQUENCE Length (SLEN) and SEQUENCE Channel Number (SCN) fields in the Control register. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 174 Parity (PAR) determines if the core uses odd or even parity. If the core detects a parity error, the received word is discarded and the Parity Error (PERR) bit in the status register is set. If the Parity GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 175: Registers
0x80000810 IRQ mask register 0x80000814 Array A base address register 0x80000818 Array B base address register 0x8000081C Transmit register 0x80000820 Receive register Table 186. GRSLINK Clock Scaler register RESERVED CLKSCALEH RESERVED CLKSCALEL 31:21 RESERVED GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 176 When the core is enabled it always outputs one NULL word before issuing the first SYNC pulse. When the core is disabled by writing ‘0’ to this bit, the SCLK clock stops within one SCLK period. Reset value: 0x00000008 Table 188. GRSLINK NULL word register RESERVED NULLWORD 31:24 RESERVED GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 177 Table 190. GRSLINK Interrupt Mask register RESERVED SERRE AERRE ROVE RNEE TNFE SRXE 31:7 RESERVED Parity Error Enable (PERRE) - When this bit is set to ‘1’ the core will generate an interrupt when a parity error is detected. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 178 RESERVED - This field is always read as zero, writes have no effect. 22:0 Fields in SLINK data word from slave to master. This register must not be read unless the Receive Not Empty (RNE) bit in the Status register is set. Reset value: Undefined GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 179: Signal Definitions
The signals are described in table 195. Table 195.Signal definitions Signal name Type Function Active Input Data into the master Output Data out of the master SLSYNC Output SLINK SYNC signal Logical 1 SLCLK Output SLINK clock Logical 1 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 180: Ascs Controller
The first pulse on the etr signal might be delayed with up to one period from the time that the core starts the synchronization interface, depending on the source used to generate the pulse. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 181: Registers
This bit is cleared by the core the cycle after is set. (Read/Write) Table 198. ETR scale register 31:28 Reserved, always zero 27:0 This field should be set to the number of system clock cycles in one ETR period. (Read/Write) GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 182 TC data. When these bits are written the core will perform a TC at the next chance it gets and send the data written. In order to not send wrong TC data the core prevents these bits from being written if the tca bit in the status register is set to ‘1’. (Read/Write) GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 183: Signal Definitions
Output TC start/stop signal Logical 1 A16HS Output Serial clock used for TC/TM Logical 1 A16DCS Output ASCS slave data out A16MAS Output TM start/stop signal Logical 1 A61ETR Output Synchronization signal Logical 1 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 184: Grtc - Telecommand Decoder
Telecommand Channel Layer (TCC) and the Telecommand Interface (TCI). Note that TCI is called AHB2TCI. A complete ECSS/CCSDS packet telecommand decoder can be realized at software level according to the latest available standards, staring from the Transfer Layer. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 185: Data Formats
[CCSDS 231.0-B-2] TC Synchronization and Channel Coding [CCSDS 232.0-B-2] TC Space Data Link Protocol [CCSDS 232.1-B-2] Communications Operation Procedure-1 [ECSS-E-ST-50-04C] Space engineering - Space data links - Telecommand protocols, synchroniza- tion and channel coding GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 186: Coding Layer (Cl)
Codeblock is corrected. A Codeblock is rejected as a Tail Sequence if more than one bit error is detected. Information regarding Count of Single Error Corrections and Count of Accept Codeblocks is provided to the FAR. Information regarding Selected Channel Input is provided via a register. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 187 E2b Channel Deactivation - selected input becomes inactive in S3 • E2c Channel Deactivation - too many codeblocks received in S3 E2d Channel Deactivation - selected input is timed-out in S3  • (design choice being: S3 => S1, abandoned frame) GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 188: Transmission
The FIFO is automatically emptied when a CLTU is either ready or has been abandoned. The reason for the latter can be codeblock error, time out etc. as described in CLTU decoding state diagram. The operational state machine is shown in figure 79. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 189 = temp1 Legend: rx_w_ptr Write pointer rx_r_ptr Read pointer Figure 79. Direct Memory Access 26.4.1 Data formatting When in the decode state, each candidate codeblock is decoded in single error correction mode as described hereafter. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 190 0x00 0x400000xx information octet8 0x00 abandoned frame 0x03 Legend: Bit [17:16] or [1:0]: “00” = continuing octet “01” = Start of Candidate Frame “10” = End of Candidate Frame “11” = Candidate Frame Abandoned GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 191: Relationship Between Buffers And Fifos
Here the previous 32-bit access will be repeated including the bytes that were previously missing, in order to fill-up the 32-bit remote memory-controller without gaps between the bytes. The receive-write-pointer shall be incremented according to the number of bytes being written to the remote memory controller. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 192 Receiver buffer full interrupt is given when the hardware pointer enters the security zone rx_w_ptr(H/W) Offset = 256 bytes rx_r_ptr (S/W) Figure 82. Buffer full interrupt (buffers size is 2 KiB in this example) GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 193: Command Link Control Word Interface (Clcw)
‘Receive buffer full’ (generated when the buffer has less than 1/8 free) (note that this interrupt is issued on a static state of the buffer, and can thus be re-issued immediately after the correspond- GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 194: Miscellaneous
1 General convention, applying to all other signals and interfaces: • Signal names are in mixed case. • An upper case '_N' suffix in the name indicates that the signal is active low. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 195: Registers
RESERVED 31: 24 SEB (Security Byte): ‘0x55’= the write will have effect (the register will be updated).  Write: Any other value= the write will have no effect on the register. Read: All zero. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 196 Automatically cleared to 0 when any other field is updated by the coding layer. Automatically set to 1 upon a read. 30: 25 RESERVED Write: Don’t care. Read: All zero. 24: 19 CAC (Count of Accept Codeblocks) (see [PSS-04-151]) Write: Don’t care. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 197 All zero. 15: 8 RFA (RF Available) Only the implemented inputs 0 through 4 are taken into account. All other bits are zero. Write: Don’t care. Read: Bit[8] = input 0, Bit[15] = input 7 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 198 RFF (RX FIFO Full) Write: Don’t care. Read: ‘0’ = FIFO not full, ‘1’ = FIFO full 6: 5 RESERVED Write: Don’t care. Read: All zero. OV (Overrun) Write: Don’t care. Read: ‘0’= nominal, ‘1’= data lost GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 199 Read: This pointer = ASR[31..24]. 23: 0 24-bit lower address pointer. This pointer contains the current RX write address. This register is incremented with the actual amount of bytes written. Power-up default: 0x00000000 Legend: GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 200 During a channel reset the register is temporarily unavailable and HRETRY response is generated if accessed. [10] It is not possible to write an out of range value to the RRP register. Such access will be ignored without an error. [11] The PSS bit usage is supported. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 201 • Pending Interrupt Register [PIR] • Interrupt Mask Register [IMR] • Pending Interrupt Clear Register [PICR] Table 219.Interrupt registers CLTU stored Input data overrun Output buffer full CLTU ready/aborted FAR available Bit Lock changed GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 202: 26.10 Signal Definitions
The signals are described in table 220. Table 220.Signal definitions Signal name Type Function Active TCACT[4:0] Input, async Active High TCLK[4:0] Input, async Bit clock Rising edge TCD[4:0] Input, async Data TCRFAVL[4:0] Input, async RF Available for CLCW High GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 203: Grtm - Ccsds Telemetry Encoder
All Frame Generation Insert Zone AMBA Attached Sync Mark Slave Reed-Solomon System clock domain Pseudo-Randomiser NRZ-M Octet clock domain Transponder Convolutional clock domain SP-L Clock Divider Sub Carrier (BPSK) GRTM Telemetry output Figure 83. Block diagram GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 204: References
Frame Header Error Control First Header Pointer Galois Field LFSR Linear Feedback Shift Register Master Channel Non Return to Zero Operational Control Field Pseudo Randomiser Procedures, Standards and Specifications Reed-Solomon Split-Phase Turbo Encoder Telemetry Virtual Channel GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 205: Layers
Pseudo-Randomiser • Convolutional coding 27.3.4 Physical Layer The Physical Layer does not differ between TM and AOS. The following functionality is implemented in the core: • Non-Return-to-Zero modulation • Split-Phase modulation • Sub-Carrier modulation GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 206: Data Link Protocol Sub-Layer
Counter (only for TM, as defined for ECSS and PSS, including the complete Transfer Frame Sec- ondary Header) and the Virtual Channel Counter Cycle (only for AOS) fields will be inserted and incremented automatically when enabled as described hereafter. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 207 The Master Channel Multiplexing Function is used to multiplex Transfer Frames of different Master Channels of a Physical Channel. Master Channel Multiplexing is performed between three sources: Master Channel Generation Service, Master Channel Frame Service and Idle Frames. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 208: Synchronization And Channel Coding Sub-Layer
• the field polynomial is x   • the code generator polynomial for E=8 is for which the highest power of x is transmitted first; • the code generator polynomial for E=16 is GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 209 This cycle is repeated until all information symbols have been received. The contents of the check symbol memory are then output from the encoder. The encoder is based on a parallel architecture, including parallel multiplier and adder. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 210 The puncturing and output sequences are defined in [CCSDS- 131.0-B-1]. The encoder also supports rate 1/2 unpunctured coding with aforementioned connection vectors and no symbol inversion. data out G1 data in data out data out G2 Figure 85. Unpuctured convolutional encoder GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 211: Physical Layer
. The divider can be configured during operation to divide the symbol rate clock frequency from 1/ º º 2 to 1/2 . The phase of the sub-carrier is programmable, selecting which phase 0 or 180 should cor- respond to a logical one on the input. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 212 Note 1: The output symbol rate for sub-carrier modulation corresponds to the rate of phases, not the frequency. Sub-carrier frequency is half the symbol rate. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 213: Connectivity
The output from the Non-Return-to-Zero Mark encoder (NRZ) can be connected to: • Convolutional encoder • Split-Phase Level modulator • Sub-Carrier modulator The input to the Convolutional Encoder (CE) can be connected to: • Packet Telemetry and AOS encoder • Reed-Solomon encoder GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 214: Operation
The wrap (WR) bit is also a control bit that should be set before transmission and it will be explained later GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 215 This tells the core that there are more active descriptors in the descriptor table. This bit should always be set when new descriptors are enabled, even if transmissions are already active. The descriptors must always be enabled before the transmit enable bit is set. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 216 The Time Strobe Interrupt (TSI) is maskable with the Transfer Frame Interrupt Enable (TFIE) bit in the DMA control register. All interrupts except Time Strobe Interrupt (TSI) are output on interrupt number 29. The Time Strobe Interrupt (TSI) is output on interrupt number 30. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 217: Registers
Transmitter AMBA Error (TA) - DMA AMBA AHB error, cleared by writing a logical 1 Transmitter Interrupt (TI) - DMA interrupt, cleared by writing a logical 1 Transmitter Error (TE) - DMA transmitter underrun, cleared by writing a logical 1 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 218 LENGTH field in the GRTM DMA length register) Table 233. GRTM configuration register (read-only) 21 20 19 18 17 16 15 14 13 12 11 10 CE SP SC DEPTH RESERVED 31: 21 RESERVED GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 219 Symbol Rate (SYMBOLRATE) - symbol rate division factor - 1 Sub Carrier Fall (SCF) -sub carrier output start with a falling edge for logical 1 14: 0 Sub Carrier Rate (SUBRATE) - sub carrier division factor - 1 GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 220 Frame Error Control Field (FECF) - transfer frame CRC enabled Frame Header Error Control (FHEC) - frame header error control enabled, only with AOS 13: 12 Version (VER) - Transfer Frame Version - “00” Packet Telemetry, “01” AOS 11: 0 RESERVED GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 221: 27.10 Signal Definitions
Bit Lock (the signals are OR-ed internally) High TCRFAVL[4:0] Input RF Available (the signals are OR-ed internally) High TMDO Output Serial bit data TMCLKO Output Serial bit data clock TMCLKI Input Transponder clock Rising GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 222: Clock Gating Unit
5. Write a 0 to the corresponding bit in the unlock register The cores connected to the clock gating unit are defined in the table below: Table 242.Clocks controlled by CLKGATE unit in the GR712RC Functional module GRETH 10/100 Mbit Ethernet MAC...
Page 223: Registers
Clock enable register 000000000110 0x80000D08 Core reset register 111111111001 After reset, the clocks for SpaceWire cores 0 and 1 are enabled to allow connection through RMAP without additional software. The remaining SpaceWire core clocks are disabled. GR712RC-UM, Jun 2017, Version 2.9 www.cobham.com/gaisler...
Page 224 Cobham; nor does the purchase, lease, or use of a product or service from Cobham convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Cobham or of third parties.

COBHAM GR712RC User Manual

1 Introduction

2 Signals and I/O Switch Matrix

3 Clocking

4 LEON3FT - High-Performance SPARC V8 32-Bit Processor

5 Fault Tolerant Memory Controller

6 On-Chip Memory with EDAC Protection

7 AHB Status Registers

8 Multiprocessor Interrupt Controller

9 Hardware Debug Support Unit

10 JTAG Debug Interface

11 General Purpose Timer Unit

12 General Purpose Timer Unit with Time Latch Capability

13 General Purpose Register

14 General Purpose I/O Port

15 UART Serial Interface

16 Spacewire Interface with RMAP Support

17 Ethernet Media Access Controller (MAC)

18 CAN Interface

19 Obsolete

20 CAN Bus Multiplexor

21 Mil-Std-1553B Bc/Rt/Bm

22 I2C-Master

23 SPI Controller

24 SLINK Serial Bus Based Real-Time Network Master

25 ASCS Controller

26 GRTC - Telecommand Decoder

27 GRTM - CCSDS Telemetry Encoder

28 Clock Gating Unit

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Summary of Contents for COBHAM GR712RC