COBHAM GR-CPCI-GR740 Quick Start Manual
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COBHAM GR-CPCI-GR740 Quick Start Manual

COBHAM GR-CPCI-GR740 Quick Start Manual

A development board based on the gr740 processor.
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GR-CPCI-GR740
A development board based on the GR740 processor.
2017 User's Manual
The most important thing we build is trust
GR-CPCI-GR740 Quick Start Guide
GR-CPCI-GR740-QSG
June 2017, Version 1.4
1
www.cobham.com/gaisler

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Summary of Contents for COBHAM GR-CPCI-GR740

  • Page 1 GR-CPCI-GR740 A development board based on the GR740 processor. 2017 User's Manual The most important thing we build is trust GR-CPCI-GR740 Quick Start Guide GR-CPCI-GR740-QSG www.cobham.com/gaisler June 2017, Version 1.4...

  • Page 2: Table Of Contents

    6.9. UART ........................23 6.10. Pin multiplexing (PROMIO/Peripherals) ................. 23 6.11. Can't boot ........................24 6.12. FTDI/JTAG ....................... 25 6.13. SDRAM not working ....................25 7. Support ..........................26 A. Default configuration ......................27 GR-CPCI-GR740-QSG www.cobham.com/gaisler June 2017, Version 1.4...

  • Page 3: Introduction

    The purpose of this document is to get users quickly started using the board. For a complete description of the board please refer to the GR-CPCI-GR740 Development Board User's Manual. The GR740 system-on-chip is described in the GR740 Data sheet and User's Manual.

  • Page 4: Board Configuration

    JTAG over FTDI and b) Ethernet. As general I/O, UART0 and UART1 are used. The complete default configuration can be found in Appendix A. If this is your first time using the GR-CPCI-GR740, please use this configuration as a starting point.

  • Page 5: Bootstrap Signals

    Bootstrap signals configure the chip on reset and are listed in section Bootstrap signals of GR740 Data sheet and User's Manual. Some of these signals can be controlled on the GR-CPCI-GR740 via the DIP switches FP-S1, FP- S2, FP-S3 and S1. The bootstrap signals that are mapped to the general purpose I/O lines (DIP switch FP-S1 and FP-S2) control settings such as the reset address for the Ethernet debug communications link (EDCL), routing of EDCL traffic, boot-PROM width and PROM EDAC enable.

  • Page 6: Pin Multiplexing

    GR-CPCI-GR740 board and the configuration on the GR740 device. First, to configure the GR-CPCI-GR740 board pin multiplexing, we need to set JP11 jumpers in the wanted config- uration. Each JP11 jumper chooses each individual pin configuration as shown in Table 2.3. Set all JP11 jumpers on position AB if full PROM/IO mode (a) is used or position BC for peripheral mode (i.e.
  • Page 7 ALTEN is used for configuration c) ). Table 2.3 shows the configuration for each bit. GPIO[15] LOW puts all bits to 1 and HIGH to 0. See section PROMIO / Interface configuration of the GR-CPCI-GR740 Development Board User's Manual and Register Bank For I/O and PLL configuration registers of the GR740 Data sheet and User's Manual.

  • Page 8: Sdram, Pci, Ethernet Port 1

    Figure 2.5. GR-CPCI-GR740 default configuration as delivered 2.6. Interfaces This section describes how to set up the main different interfaces of the GR-CPCI-GR740. If you are not interested on a specific interface not used on the default configuration, skip that part.

  • Page 9: Jtag Ftdi

    2.6.2. Ethernet There are two ethernet ports available in the GR-CPCI-GR740, port 0 and port 1. To use port 1, make sure that the pin multiplexing is configured to use ETH1, as explained in Section 2.5. FP-S3-7 chooses between gigabit mode and 100 Mbps.

  • Page 10: Uarts

    PCBs provided for each type of PCI configuration. The plug-on PCB's 24, 25, 26 and 27 have to be plugged on the J24, J25, J26 and J27 on the back of the GR-CPCI-GR740 respectively.

  • Page 11: Comments On System-On-Chip Design

    AHB bridge. This has no impact for normal memory accesses but existing software may not support AMBA plug and play scanning over the AHB-to-AHB bridges. All recent versions of operating systems distributed by Cobham Gaisler will correctly detect the peripheral devices in GR740. Support for recursive plug and play scanning over bridges is present in BCC version 1.0.41 (software compiled by earlier versions of BCC need to have been built...

  • Page 12: Grmon2 Hardware Debugger

    The first step is to set up a debug link in order to connect to the board. The following section outlines which debug interfaces are available and how to use them on the GR-CPCI-GR740 CompactPCI Development Board, after that a basic first inspection of the board is exemplified.

  • Page 13: Connecting Via Spacewire Rmap Interface

    The previous sections have described which debug-links are available and how to start using them with GRMON2. The subsections below assume that GRMON2, the host computer and the GR-CPCI-GR740 board have been set up so that GRMON2 can connect to the board.
  • Page 14 AHB-to-AHB Bridge Cobham Gaisler LEON4 Debug Support Unit Cobham Gaisler AHB/APB Bridge Cobham Gaisler AMBA Trace Buffer Cobham Gaisler AHB/APB Bridge Cobham Gaisler AHB/APB Bridge Cobham Gaisler Muxed FT DDR/SDRAM controller Cobham Gaisler Memory controller with EDAC Cobham Gaisler GRPCI2 PCI/AHB bridge...
  • Page 15 AHB: 00000000 - 80000000 AHB: F0000000 - F0400000 AHB: FFE00000 - FFF00000 IRQ: 28 L2C: 4-ways, cachesize: 2048 kbytes, mtrr: 16, FT, AHB SPLIT support memscrub0 Cobham Gaisler AHB Memory Scrubber AHB Master 1 AHB: FFE01000 - FFE01100 IRQ: 28...
  • Page 16 Cobham Gaisler General Purpose I/O port APB: FF902000 - FF902100 IRQ: 16 irqmp0 Cobham Gaisler Multi-processor Interrupt Ctrl. APB: FF904000 - FF908000 EIRQ: 10 gptimer0 Cobham Gaisler Modular Timer Unit APB: FF908000 - FF908100 IRQ: 1 16-bit scalar, 5 * 32-bit timers, divisor 250...
  • Page 17 Cobham Gaisler General Purpose Register Bank APB: FFA0B000 - FFA0B100 adev51 Cobham Gaisler CCSDS TDP / SpaceWire I/F APB: FFA0C000 - FFA0C200 IRQ: 31 l4stat1 Cobham Gaisler LEON4 Statistics Unit APB: FFA0D000 - FFA0D200 cpus: 4, counters: 16, i/f index: 1...
  • Page 18 | GRCAN | CAN core 0 & 1 | L4STAT | LEON4 Statistics | APBUART | UART 0 | APBUART | UART 1 | SPICTRL | SPI Controller | MCTRL | PROM/IO +------+----------+----------------------------+----------+---------+-------+ grmon2> GR-CPCI-GR740-QSG www.cobham.com/gaisler June 2017, Version 1.4...

  • Page 19: Board Package

    The first step in creating a boot-PROM image for GR-CPCI-GR740 is to compile the bdinit.c file. This is done with the command sparc-elf-gcc -O2 -c -o bdinit.o gr-cpci-gr740-bp/MKPROM2/bdinit.c. Note that this requires the Bare-C Compiler (BCC) available from http://www.gaisler.com.
  • Page 20 Image of /home/ag/hello.prom verified without errors grmon2> flash Intel-style 8-bit flash on D[31:24] Manuf. : Intel Device : MT28F640J3 Device ID : 96ff440a0000403f User ID : ffffffffffffffff 1 x 8 Mbytes = 8 Mbytes total @ 0xc0000000 GR-CPCI-GR740-QSG www.cobham.com/gaisler June 2017, Version 1.4...
  • Page 21 PROM width selection made via the bootstrap signal GPIO[10] and the setting of jumper JP6f on the board. See section 4.5.4 of the GR-CPCI-GR740 Development Board User's Manual. • In case the PROM has been programmed with a destructive application it is possible to prevent the processor's from starting up by holding the RESET and BREAK buttons on the front-panel, and then releasing RESET will still pressing BREAK.

  • Page 22: Frequently Asked Questions / Common Mistakes / Know Issues

    0 0x07ffffff. The scrubber monitors the Memory AHB bus for errors reported by the memory controller. The command scrub shows the status: grmon2> scrub AHB status register: Not triggered Scrubber status: Done init 00000000-0fffffff GR-CPCI-GR740-QSG www.cobham.com/gaisler June 2017, Version 1.4...

  • Page 23: Flash Programming

    This will have the side effect of toggling the interface IO lines according to the address driven to the PROM during the decompression phase which might cause unwanted interface communication. For 1553 this has been solved by making the TX-inhibit lines non-multiplexed which will prevent any 1553 data from going out. GR-CPCI-GR740-QSG www.cobham.com/gaisler June 2017, Version 1.4...

  • Page 24: Can't Boot

    GPIOs to drive an enable signal to those IO interfaces transceivers to disable them during boot. Please note that this is not supported currently on the GR-CPCI-GR740 development board.

  • Page 25: Ftdi/Jtag

    Try removing a little bit of the plastic protection and see if that works. Figure 6.1. GR-CPCI-GR740 GPIO J4 connection. 6.13. SDRAM not working If the SDRAM is not working. Check the following things: •...

  • Page 26: Support

    7. Support For support contact the Cobham Gaisler support team at support@gaisler.com. When contacting support, please identify yourself in full, including company affiliation and site name and address. Please identify exactly what product that is used, specifying if it is an IP core (with full name of the library distribution archive file), component, software version, compiler version, operating system version, debug tool version, simulator tool version, board version, etc.

  • Page 27: Default Configuration

    Appendix A. Default configuration This appendix describes the jumper and switch positions for the default configuration of the board. See section Setting Up and Using the Board on the GR-CPCI-GR740 Development Board User's Manual. Table A.1. Jumper configuration Jumper Default configuration Connected.
  • Page 28 Default configuration FP-S2-2 Pull-up. FP-S2-3 Pull-down. FP-S2-4 Pull-up. FP-S2-5 Pull-up. FP-S2-6 Pull-up. FP-S2-7 Pull-down. FP-S2-8 Pull-down. FP-S3-1 Open. FP-S3-2 Open. FP-S3-3 Closed. FP-S3-4 Closed. FP-S3-5 Closed. FP-S3-6 Open. FP-S3-7 Closed. FP-S3-8 Open. Right position. GR-CPCI-GR740-QSG www.cobham.com/gaisler June 2017, Version 1.4...
  • Page 29 Cobham convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Cobham or of third parties. All information is provided as is. There is no warranty that it is correct or suitable for any purpose, neither implicit nor explicit.

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