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1.3.2
ASIC
(1) Oscillator circuit
Generates the main clock for the CPU by deviding the source clock frequency
into two.
(2) Address decoder
Generates the CS for each device.
(3) DRAM control
Generates the RAS, CAS, WR, OE and MA signals for the DRAM and controls
refresh processing (CAS before RAS self-refreshing method).
(4) Interrupt control
Interrupt levels:
Priority High
(5) Timers
The following timers are incorporated:
Timer 1
Timer 2
Timer 3
Timer 4
(6) FIFO
A 2,560-bit FIFO is incorporated. Data for one raster is transfered from the RAM
to the FIFO by DMA transmission and is out put as serial video data. The data
cycle is 1.53 MHz.
(7) CDCC parallel I/O
CDCC data is received in 4-byte units by DMA transmission. If data of less than
4 bytes remains, a time-out occurs and it is forcibly transferred by DMS transfer.
Low Speed Mode
STROBE
BUSY
ACK
High Speed Mode
STROBE
BUSY
ACK
7
NMI
6
FIFO
5
Timer1
4
BD
3
EXINT (Option Serial I/O)
2
CDCC
Low
1
Timer2
16-bit timer
10-bit timer
Watch-dog timer 1
Watch-dog timer 2
3 µ sec
t < 33 µ sec
0.6 µ sec
Fig. 2.4
II - 4
t > 33 µ sec
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Troubleshooting
