........................Read This First ......................About This Manual ....................How to Use This Manual ................Information About Cautions and Warnings ..............Related Documentation from Texas Instruments ..........................Overview ........................EVM Features ....................PCI Express Connector ......................PCI Add-In Slots .......................
SCPU031 – February 2009 XIO2001 Evaluation Module (EVM) Read This First About This Manual This manual describes the operation of the XIO2001 evaluation module (EVM) from Texas Instruments. How to Use This Manual This document contains the following sections: •...
100-Ω differential impedance (50-Ω single-ended) using standard routing guidelines and requirements . Power for the XIO2001 EVM and any PCI add-in card connected to the EVM is provided or derived from the standard voltages provided on the PCI Express connector. Power for the 3.3-V rail is provided directly from the add-in connector, 5-V and 12-V is provided from the IDE power connector, while regulators are present to derive 1.5-V for the XIO2001 and -12-V for the PCI connectors.
Pin 9 on the J1 header is a global reset (GRST ) for the XIO2001. Driving this pin low will cause all registers and state machines within the XIO2001 to return to a default power-up state. This pin generally must remain disconnected.
Pin 8 on header J1 is CLKREQ for the XIO2001. Driving this pin low will allow the REFCLK to stop when the XIO2001 is in PCI PM L1. The CLKREQ protocol as described in the PCI Express Base Specification and Express Card standard is supported.
As the x16 PCI express add-in slots are designed as a graphics expansion port, many only support a single interrupt (INTA ), as this is the only interrupt that will be required by a graphics card. The XIO2001 EVM supports all interrupts and balances interrupt loading by rotating the interrupts to each add-in slot as required by the PCI Local Bus Specification.
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Unsupported Request. Any transactions initiated on the secondary side of the bus that fall within this range will not be claimed by the bridge. The I/O window for the XIO2001 has a minimum size of 4 KBytes and is naturally 4K-aligned. Typically, most systems use only 16-bit addressing for I/O transactions, so the upper base and limit registers remain 0.
If 64-bit addressing is desired and the memory window for devices behind the XIO2001 resides all or in part in 64-bit memory space then the prefetchable base upper 32-bit register will combine with the prefetchable base register and the prefetchable limit upper 32-bit register will combine with the prefetchable limit register to create 64-bit base and limit registers.
EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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