Lattice iCE40 Ultra User Manual page 7

Figure 4. Key-socket Arrangement
Pin assignments iCE40 Ultra FPGA
Table 2 lists the complete pin assignments for the iCE40 Ultra FPGA for the different keys and other hard wired
peripherals on the board
Table 2. Pin Assignment
Pin
Number Pin Name
A4 VCCIO_0
B5 IOT_46B_G0
A6 RGB2
B6 RGB1
C6 RGB0
A2 IRLED
A1 VSSIO_LED
C3 SPI_VCCIO1
D1 IOB_33B_SI_M
OSI_SPI1
F2 IOB_32A_SO_
MISO_SPI1
E1 IOB_34A_SCK_
SCK_SPI1
F1 IOB_35B_SS_
MCSNO_SPI1
E4 IOB_12A_G4_C
DONE
D3 CRESET_B
B2 IOB_31B
C1 IOB_30A
E2 IOB_29B
D2 IOB_27B
B1 IOB_26A
E3 IOB_20A
iCE40 Ultra Mobile Development Platform User Guide
Pin Assignment for
Bank Default Key A
Bank 0 3V3
Bank 0 Not used / Optional ext
SMA clock
Bank 0 BLED (RGB LED)
Bank 0 GLED (RGB LED)
Bank 0 RLED (RGB LED)
Bank 0 HPLED (IRLED or VLED) HPLED (IRLED or VLED
Bank 0 GND
Bank 1 3V3
Bank 1 ICE_SI/FLSH_MOSI
Bank 1 ICE_SO/FLSH_MISO
Bank 1 FLSH_SCLK
Bank 1 FLSH_CS
Bank 1 CDONE
Bank 1 CRESET
Bank 1 HALL_OUT/BMP_XCLR
Bank 1 PoolA_Sensor_SDA
Bank 1 Pool_Sensor_SCL
Bank 1 CLK_STNDBY#
(Osc. Standby)
Bank 1 FP_RSTn
(Fingerprint reset)
Bank 1 UART_TX (BLE)
Orient the direction of the key
using these arrows
Pin Assignment for
Key B
3V3
Not used / Optional ext
SMA clock
BLED (RGB LED)
GLED (RGB LED)
RLED (RGB LED)
GND
3V3
ICE_SI/FLSH_MOSI
ICE_SO/FLSH_MISO
FLSH_SCLK
FLSH_CS
CDONE
CRESET
HALL_OUT/BMP_XCLR
PoolA_Sensor_SDA
Pool_Sensor_SCL
CLK_STNDBY#
(Osc. Standby)
FP_RSTn
(Fingerprint reset)
UART_TX (BLE)
7
Pin Assignment for
Key C
3V3
I2S_WS1 (Microphone 1
(DP R51))
I2S_CE1 (Microphone 1)
I2S_SCK1 (Microphone
1)
I2S_SD1 (Microphone 1)
HPLED (IRLED or VLED
GND
3V3
ICE_SI/FLSH_MOSI
ICE_SO/FLSH_MISO
FLSH_SCLK
FLSH_CS
CDONE
CRESET
HALL_OUT/BMP_XCLR
PoolA_Sensor_SDA
Pool_Sensor_SCL
CLK_STNDBY#
(Osc. Standby)
FP_RSTn (
Fingerprint reset)
UART_TX (BLE)