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SupIRBuck
USER GUIDE FOR IRDC3863 EVALUATION BOARD
DESCRIPTION
The IR3863 SupIRBuck
fully integrated and highly efficient DC/DC
voltage regulator. The onboard constant on
time hysteretic controller and MOSFETs make
IR3863 a space-efficient solution that delivers
up to 6A of precisely controlled output voltage
in a 4mm x 5mm QFN package.
In addition to excellent light load and full load
efficiency, the IR3863 offers features such as:
a 0.5V reference, programmable switching
frequency, temperature compensated over
current protection, thermal shutdown and
optional forced continuous conduction mode.
BOARD FEATURES
V
= +12V
IN
V
= +5V
CC
V
= +1.05V
OUT
I
= 0 to 6A
OUT
F
= 300kHz @ CCM
S
L = 2.2µH
C
= 22µF (ceramic 1210) + 68µF (electrolytic)
IN
C
= 47µF (ceramic 0805) + 150µF (PC-CON)
OUT
TM
is an easy-to-use,
TM
Additional features include: pre-bias startup,
soft start, power good output, enable input with
voltage monitoring capability and over/under
voltage protection, making the device a very
flexible solution that is suitable for a broad
range of applications.
This user guide contains the schematic, bill of
materials, and operating instructions of the
IRDC3863 evaluation board. Detailed product
specifications,
application
performance curves at different operating
conditions are available in the IR3863 data
sheet.
IRDC3863
information
and
1

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Summary of Contents for International Rectifier SupIRBuck IRDC3863

  • Page 1 IRDC3863 SupIRBuck USER GUIDE FOR IRDC3863 EVALUATION BOARD DESCRIPTION The IR3863 SupIRBuck is an easy-to-use, Additional features include: pre-bias startup, fully integrated and highly efficient DC/DC soft start, power good output, enable input with voltage regulator. The onboard constant on voltage monitoring capability and over/under time hysteretic controller and MOSFETs make voltage protection, making the device a very...
  • Page 2 IRDC3863 CONNECTIONS and OPERATING INSTRUCTIONS An input supply in the range of 7 to 16V should be connected from VIN to PGND. A maximum load of 6A may be connected to V and PGND. The connection diagram is shown in Fig. 1, and the inputs and outputs of the board are listed in Table 1.
  • Page 3: Connection Diagram

    IRDC3863 CONNECTION DIAGRAM GROUND Control Switch for: FCCM GROUND VCC = +5.0V VOUT = +1.05V GROUND Fig. 1: Connection Diagram of IRDC3863 Evaluation Board...
  • Page 4: Pcb Board Layout

    IRDC3863 PCB Board Layout Fig. 2: Board Layout, Top Components Fig. 3: Board Layout, Bottom Components...
  • Page 5 IRDC3863 PCB Board Layout Fig. 4: Board Layout, Top Layer Fig. 5: Board Layout, Bottom Layer...
  • Page 6 IRDC3863 PCB Board Layout Fig. 6: Board Layout, Mid-layer I Fig. 7: Board Layout, Mid-layer II...
  • Page 7 IRDC3863...
  • Page 8: Bill Of Materials

    IRDC3863 Bill of Materials...
  • Page 9 IRDC3863 TYPICAL OPERATING WAVEFORMS Tested with demoboard shown in Fig. 8, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, T = 25 C, no airflow, unless otherwise specified PGOOD PGOOD VOUT VOUT 5V/div 5V/div 1V/div 500mV/div 5ms/div 5V/div 5V/div...
  • Page 10: Typical Performance

    IRDC3863 TYPICAL OPERATING WAVEFORMS Tested with demoboard shown in Fig. 8, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, T = 25 C, no airflow, unless otherwise specified VOUT VOUT PHASE PHASE 50mV/div 50mV/div 10V/div 50µs/div 10V/div 2A/div 50µs/div...
  • Page 11 IRDC3863 TYPICAL OPERATING DATA VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, IOUT = 0 ~ 6A, T = 25 C, no airflow, unless otherwise specified 0.01 Load Current (A) Load Current (A) Fig. 18: Efficiency vs. Load Current Fig.
  • Page 12 IRDC3863 PCB Metal and Components Placement Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large toe fillet that can be easily inspected.
  • Page 13 IRDC3863 Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist misalignment.
  • Page 14: Stencil Design

    IRDC3863 Stencil Design The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad, the part will float and the lead lands will open.
  • Page 15 IRDC3863 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 06/2011...

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