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International Rectifier IR3821 User Manual

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SupIRBuck
USER GUIDE FOR IR3821 EVALUATION BOARD
DESCRIPTION
The
IR3821
is
a
converter,
providing
performance and flexible solution in a small
5mmx6mm Power QFN package.
Key features offered by the IR3821 include
programmable soft-start ramp, precision
0.6V
reference
voltage,
,
Power Good
thermal protection, fixed
600kHz switching frequency requiring
external component, input under-voltage
lockout for proper start-up, and pre-bias
start-up.

BOARD FEATURES

•
V
= +12V (13.2V Max)
in
•
V
= +1.8V @ 0- 7A
out
•
L=1.0uH
•
C
=3x10uF (ceramic 1206) + 330uF (electrolytic)
in
•
C
=6x22uF (ceramic 0805)
out
Rev 0.1
01/07/2008
TM
synchronous
buck
a
compact,
high
programmable
no
An output over-current protection function is
implemented by sensing the voltage developed
across the on-resistance of the synchronous
rectifier
MOSFET
performance.
This user guide contains the schematic and bill
of materials for the IR3821 evaluation board.
The guide describes operation and use of the
evaluation board itself. Detailed
information for IR3821 is available in the
IR3821 data sheet.
IRDC3821
for
optimum
cost
application
and
1

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Summary of Contents for International Rectifier IR3821

  • Page 1: Board Features

    MOSFET optimum cost 5mmx6mm Power QFN package. performance. Key features offered by the IR3821 include This user guide contains the schematic and bill programmable soft-start ramp, precision of materials for the IR3821 evaluation board. 0.6V reference voltage,...
  • Page 2 Table I. IR3821 has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). These inputs are connected on the board with a zero ohm resistor (R15). Separate supplies can be applied to these inputs.
  • Page 3 IRDC3821 Connection Diagram = +12v GROUND GROUND GROUND = +1.8v Good Fig. 1: Connection diagram of IR3821 evaluation board Rev 0.1 01/07/2008...
  • Page 4 IRDC3821 Fig. 2: Board layout, top overlay Fig. 3: Board layout, bottom overlay (rear view) Rev 0.1 01/07/2008...
  • Page 5 IRDC3821 Fig. 4: Board layout, mid-layer I AGND PGND Plain Plain Single point connection between AGND and PGND. Fig. 5: Board layout, mid-layer II Rev 0.1 01/07/2008...
  • Page 6 IRDC3821 Rev 0.1 01/07/2008...

  • Page 7: Bill Of Materials

    R14, R17 Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW060310K0FKEA 3.09K Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW06033K09FKEA 600kHz, 7A, SupIRBuck International IR3821 5x6mm IR3821 Module Rectifier Banana Jack, Insulated Johnson 105-0853-001 Solder Terminal, Black Components Banana Jack- Insulated Johnson 105-0852-001...
  • Page 8 IRDC3821 TYPICAL OPERATING WAVEFORMS Vin=Vcc=12.0V, Vo=1.8V, Io=0-7A, Room Temperature, No Air Flow PGood Iout Vout Vout Fig. 7: Start up at 7A Load Fig. 8: Start up at 7A Load, , Ch , Ch , Ch , Ch , Ch , Ch PGood Fig.
  • Page 9 IRDC3821 TYPICAL OPERATING WAVEFORMS Vin=Vcc=12V, Vo=1.8V, Io=3.5A-7A, Room Temperature, No Air Flow Fig. 13: Transient Response, 3.5A to 7A step , Ch Rev 0.1 01/07/2008...
  • Page 10 IRDC3821 TYPICAL OPERATING WAVEFORMS Vin=Vcc=12V, Vo=1.8V, Io=7A, Room Temperature, No Air Flow Fig. 14: Bode Plot at 7A load shows a bandwidth of 62 kHz and phase margin of 51 degrees Rev 0.1 01/07/2008...
  • Page 11 IRDC3821 TYPICAL OPERATING WAVEFORMS Vin=12V, Vo=1.8V, Io=0-7A, Room Temperature, No Air Flow Load Current (A) Efficiency VCC=VIN=12V Efficiency VIN=12V@VCC=5V Fig.15: Efficiency versus load current Load Current (A) Power Loss VCC=VIN=12V Power Loss VIN = 12V@VCC = 5V Fig.16: Power loss versus load current Rev 0.1 01/07/2008...
  • Page 12 IRDC3821 THERMAL IMAGES Vin=Vcc=12V, Vo=1.8V, Io=7A, Room Temperature, No Air Flow Fig. 17: Thermal Image at 7A load Test point 1 is the IR3821 Rev 0.1 01/07/2008...
  • Page 13 IRDC3821 PCB Metal and Components Placement The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to the maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large and inspectable toe fillet.
  • Page 14 IRDC3821 Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis-alignment.

  • Page 15: Stencil Design

    IRDC3821 Stencil Design • The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will be open.
  • Page 16 IRDC3821 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Consumer market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 11/07 Rev 0.1 01/07/2008...